AD9772A
FUNCTIONAL DESCRIPTION
Table II. Digital Modes
Digital
Mode
MOD0
MOD1
Digital
Filter
Zero-
Stuffing
Figure 4 shows a simplified block diagram of the AD9772A.
The AD9772A is a complete, 2 oversampling, 14-bit DAC that
includes a 2 interpolation filter, a phase-locked loop (PLL)
clock multiplier and a 1.20 V bandgap voltage reference. While
the AD9772A’s digital interface can support input data rates as
high as 160 MSPS, its internal DAC can operate up to 400 MSPS,
thus providing direct IF conversion capabilities. The 14-bit DAC
provides two complementary current outputs whose full-scale
current is determined by an external resistor. The AD9772A
features a flexible, low jitter, differential clock input providing
excellent noise rejection while accepting a sine wave input. An
on-chip PLL clock multiplier produces all of the necessary
synchronized clocks from an external reference clock source.
Separate supply inputs are provided for each functional block to
ensure optimum noise and distortion performance. A SLEEP
mode is also included for power savings.
CLKCOM CLKVDD MOD0 MOD1 RESET PLLLOCK DIV0 DIV1
CLK+
CLK–
1
1 /2
Baseband
Baseband
Direct IF
Direct IF
0
0
1
1
0
1
0
1
Low
Low
High
High
No
Yes
No
Yes
AD9772A
CLOCK DISTRIBUTION
AND MODE SELECT
FILTER
MUX
CONTROL CONTROL
PLL CLOCK
MULTIPLIER
2 /4
PLLCOM
LPF
PLLVDD
Applications requiring the highest dynamic range over a wide
bandwidth should consider operating the AD9772A in a baseband
mode. Note, the “zero-stuffing” option can also be used in this
mode although the ratio of signal to image power will be reduced.
Applications requiring the synthesis of IF signals should con-
sider operating the AD9772A in a Direct IF mode. In this case,
the “zero-stuffing” option should be considered when synthesiz-
ing and selecting IFs beyond the input data rate, f
DATA
. If the
reconstructed IF falls below f
DATA
, the “zero-stuffing” option
may or may not be beneficial. Note, the dynamic range (i.e.,
SNR/SFDR) is also optimized by disabling the PLL Clock Mul-
tiplier (i.e., PLLVDD to PLLCOM) and using an external low
jitter clock source operating at the DAC update rate, f
DAC
.
2
Interpolation Filter Description
DATA
INPUTS
(DB13...
DB0)
SLEEP
EDGE-
TRIGGERED
LATCHES
2 FIR
INTER-
POLATION
FILTER
ZERO
STUFF
MUX
I
OUTA
14-BIT DAC
I
OUTB
REFIO
FSADJ
+1.2V REFERENCE
AND CONTROL AMP
DCOM DVDD
ACOM AVDD
REFLO
Figure 4. Functional Block Diagram
Preceding the 14-bit DAC is a 2 digital interpolation filter that
can be configured for a low-pass (i.e., baseband mode) or high-
pass (i.e., direct IF mode) response. The input data is latched
into the edge-triggered input latches on the rising edge of the
differential input clock as shown in Figure 1a and then interpo-
lated by a
factor of two
by the digital filter. For traditional baseband
applications, the 2 interpolation filter has a low-pass response.
For direct IF applications, the filter’s response can be converted
into a high-pass response to extract the higher image. The output
data of the 2 interpolation filter can update the 14-bit DAC
directly or undergo a “zero-stuffing” process to increase the DAC
update rate by another
factor of two.
This action enhances the
relative signal level and passband flatness of the higher images.
DIGITAL MODES OF OPERATION
The 2 interpolation filter is based on a 43-tap half-band sym-
metric FIR topology that can be configured for a low- or
high-pass response, depending on the state of the MOD0
control input. The low-pass response is selected with MOD0
LOW while the high-pass response is selected with MOD0
HIGH. The low-pass frequency and impulse response of the
half-band interpolation filter are shown in Figures 2a and 2b,
while Table I lists the idealized filter coefficients. Note, a FIR
filter’s impulse response is also represented by its idealized
filter coefficients.
The 2× interpolation filter essentially multiplies the input data
rate to the DAC by a factor of two, relative to its original input
data rate, while simultaneously reducing the magnitude of the
first image associated with the original input data rate occurring
at f
DATA
– f
FUNDAMENTAL
. Note, as a result of the 2 interpola-
tion, the digital filter’s frequency response is uniquely defined
over its Nyquist zone of dc to f
DATA
, with mirror images occur-
ring in adjacent Nyquist zones.
The benefits of an interpolation filter are clearly seen in Fig-
ure 5, which shows an example of the frequency and time
domain representation of a discrete time sine wave signal before
and after it is applied to the 2 digital interpolation filter in a
low-pass configuration. Images of the sine wave signal appear
around multiples of the DAC’s input data rate (i.e., f
DATA
) as
predicted by sampling theory. These undesirable images will
also appear at the output of a reconstruction DAC, although
attenuated by the DAC’s sin(x)/x roll-off response.
In many bandlimited applications, the images from the recon-
struction process must be suppressed by an analog filter following
the DAC. The complexity of this analog filter is typically deter-
mined by the proximity of the desired fundamental to the first
image and the required amount of image suppression. Adding to
the complexity of this analog filter may be the requirement of
compensating for the DAC’s sin(x)/x response.
The AD9772A features four different digital modes of operation
controlled by the digital inputs, MOD0 and MOD1. MOD0
controls the 2 digital filter’s response (i.e., low-pass or high-
pass), while MOD1 controls the “zero-stuffing” option. The
selected mode as shown in Table II will depend on whether the
application requires the reconstruction of a baseband or IF signal.
REV. A
–11–
AD [ ANALOG DEVICES ]
