AD9708
FUNCTIONAL DESCRIPTION
Figure 12 shows a simplified block diagram of the AD9708. The
AD9708 consists of a large PMOS current source array capable of
providing up to 20 mA of total current. The array is divided into
31 equal currents that make up the five most significant bits
(MSBs). The remaining 3 LSBs are also implemented with equally
weighted current sources whose sum total equals 7/8th of an
MSB current source. Implementing the upper and lower bits
with current sources helps maintain the DAC’s high output
impedance (i.e. > 100 kΩ). All of these current sources are
switched to one or the other of the two output nodes (i.e., IOUTA
or IOUTB) via PMOS differential current switches. The switches
are based on a new architecture that drastically improves
distortion performance.
The analog and digital sections of the AD9708 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 volt to 5.5 volt range. The digital section,
which is capable of operating up to a 125 MSPS clock rate,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V bandgap
voltage reference and a reference control amplifier.
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, R
SET
. The external resistor, in combination with
both the reference control amplifier and voltage reference
V
REFIO
, sets the reference current I
REF
, which is mirrored over to
the segmented current sources with the proper scaling factor.
The full-scale current, I
OUTFS
, is thirty-two times the value of I
REF
.
DAC TRANSFER FUNCTION
As previously mentioned, I
OUTFS
is a function of the reference
current I
REF
, which is nominally set by a reference voltage
V
REFIO
and external resistor R
SET
. It can be expressed as:
I
OUTFS
= 32
×
I
REF
where
I
REF
=
V
REFIO
/R
SET
(4)
The two current outputs will typically drive a resistive load
directly. If dc coupling is required, IOUTA and IOUTB should
be directly connected to matching resistive loads, R
LOAD
, which
are tied to analog common, ACOM. Note, R
LOAD
may repre-
sent the equivalent load resistance seen by IOUTA or IOUTB
as would be the case in a doubly terminated 50
Ω
or 75
Ω
cable.
The single-ended voltage output appearing at the IOUTA and
IOUTB nodes is simply:
V
OUTA
=
I
OUTA
×
R
LOAD
V
OUTB
=
I
OUTB
×
R
LOAD
(5)
(6)
(3)
Note the full-scale value of V
OUTA
and V
OUTB
should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
The differential voltage, V
DIFF
, appearing across IOUTA and
IOUTB is:
V
DIFF
= (I
OUTA
– I
OUTB
)
×
R
LOAD
(7)
Substituting the values of I
OUTA
, I
OUTB
, and I
REF
; V
DIFF
can be
expressed as:
V
DIFF
= {(2
DAC CODE
– 255)/256}/
×
(32
R
LOAD
/R
SET
)
×
V
REFIO
VOLTAGE REFERENCE AND CONTROL AMPLIFIER
(8)
The AD9708 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current output,
I
OUTFS
, when all bits are high (i.e., DAC CODE = 255), while
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB are a function
of both the input code and I
OUTFS
and can be expressed as:
I
OUTA
= (DAC
CODE/256)
×
I
OUTFS
I
OUTB
= (255 –
DAC CODE)/256
×
I
OUTFS
(1)
(2)
where
DAC CODE
= 0 to 255 (i.e., Decimal Representation).
The AD9708 contains an internal 1.20 V bandgap reference
that can be easily disabled and overridden by an external refer-
ence. REFIO serves as either an
input
or
output
depending on
whether the internal or an external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 13, the internal
reference is activated and REFIO provides a 1.20 V output. In
this case, the internal reference
must
be compensated externally
with a ceramic chip capacitor of 0.1
µF
or greater from REFIO
to REFLO. Note that REFIO is not designed to drive any ex-
ternal load. It should be buffered with an external amplifier
having an input bias current less than 100 nA if any additional
loading is required.
+5V
0.1 F
REFLO
+1.20V REF
V
REFIO
0.1 F
R
SET
2k
I
REF
REFIO
FS ADJ
COMP1
50pF
AVDD
ACOM
AD9708
CURRENT
SOURCE
ARRAY
COMP2
0.1 F
V
DIFF
= V
OUTA
– V
OUTB
+5V
DVDD
DCOM
SEGMENTED
SWITCHES
LATCHES
SLEEP
DIGITAL DATA INPUTS (DB7–DB0)
IOUTA
IOUTB
I
OUTA
I
OUTB
V
OUTB
R
LOAD
50
V
OUTA
R
LOAD
50
CLOCK
CLOCK
Figure 12. Functional Block Diagram
REV. B
–7–
AD [ ANALOG DEVICES ]
