AD9513
DELAY BLOCK
OUTPUTS
OUT2 includes an analog delay element that gives variable time
delays (ΔT) in the clock signal passing through that output.
Each of the three AD9513 outputs can be selected either as
LVDS differential outputs or as pairs of CMOS single-ended
outputs. If selected as CMOS, the OUT is a noninverted, single-
ended output, and OUTB is an inverted, single-ended output.
CLOCK INPUT
OUT1 ONLY
÷N
ØSELECT
3.5mA
LVDS
CMOS
∆T
OUTPUT
DRIVER
OUT
FINE DELAY ADJUST
(16 STEPS)
FULL SCALE : 1.5ns, 5ns, 10ns
OUTB
Figure 25. Analog Delay Block
The amount of delay that can be used is determined by the
output frequency. The amount of delay is limited to less than
one-half cycle of the clock period. For example, for a 10 MHz
clock, the delay can extend to the full 11.6 ns maximum. However,
for a 100 MHz clock, the maximum delay is less than 5 ns (or
half of the period).
3.5mA
Figure 26. LVDS Output Simplified Equivalent Circuit
V
S
The AD9513 allows for the selection of three full-scale delays,
1.8 ns, 6.0 ns, and 11.6 ns, set by delay full-scale (see Table 11).
Each of these full-scale delays can be scaled by 16 fine
OUT1/
OUT1B
adjustment values, which are set by the delay word (see Table 13).
The delay block adds some jitter to the output. This means that
the delay function should be used primarily for clocking digital
chips, such as FPGA, ASIC, DUC, and DDC, rather than for
supplying a sample clock for data converters. The jitter is higher
for longer full scales because the delay block uses a ramp and
trip points to create the variable delay. A longer ramp means
more noise has a chance of being introduced.
Figure 27. CMOS Equivalent Output Circuit
When the delay block is OFF (bypassed), it is also powered
down.
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