AD9513
3.3V
3.1V
FUNCTIONAL DESCRIPTION
2.2V
OVERALL
35ms
MAX
The AD9513 provides for the distribution of its input clock on
up to three outputs. Each output can be set to either LVDS or
CMOS logic levels. Each output has its own divider that can be
set for a divide ratio selected from a list of integer values from
1 (bypassed) to 32.
V
S
0V
CLK
OUT
CLOCK FREQUENCY
IS EXAMPLE ONLY
DIVIDE = 2
PHASE = 0
< 65ms
OUT2 includes an analog delay block that can be set to add an
additional delay of 1.8 ns, 6.0 ns, or 11.6 ns full scale, each with
16 levels of fine adjustment.
INTERNAL SYNC NODE
Figure 19. Power-On Sync Timing
SYNCB
CLK, CLKB—DIFFERENTIAL CLOCK INPUT
If the setup configuration of the AD9513 is changed during
operation, the outputs can become unsynchronized. The
outputs can be resynchronized to each other at any time.
Synchronization occurs when the SYNCB pin is pulled low and
released. The clock outputs (except where divide = 1) are forced
into a fixed state (determined by the divide and phase settings)
and held there in a static condition, until the SYNCB pin is
returned to high. Upon release of the SYNCB pin, after four
cycles of the clock signal at CLK, all outputs continue clocking
in synchronicity (except where divide = 1).
The CLK and CLKB pins are differential clock input pins.
This input works up to 1600 MHz. The jitter performance is
degraded by a slew rate below 1 V/ns. The input level should be
between approximately 150 mV p-p to no more than 2 V p-p.
Anything greater can result in turning on the protection diodes
on the input pins.
See Figure 18 for the CLK equivalent input circuit. This input
is fully differential and self-biased. The signal should be ac-
coupled using capacitors. If a single-ended input must be used,
this can be accommodated by ac coupling to one side of the
differential input only. The other side of the input should be
bypassed to a quiet ac ground by a capacitor.
When divide = 1 for an output, that output is not affected by
SYNCB.
3 CLK CYCLES
4 CLK CYCLES
CLOCK INPUT
STAGE
CLK
OUT
V
S
EXAMPLE: DIVIDE ≥ 8
EXAMPLE DIVIDE
RATIO PHASE = 0
PHASE = 0
CLK
SYNCB
Figure 20. SYNCB Timing with Clock Present
CLKB
4 CLK CYCLES
2.5kΩ
5kΩ
2.5kΩ
CLK
§
§
§
EXAMPLE DIVIDE
RATIO PHASE = 0
DEPENDS ON PREVIOUS STATE
OUT
5kΩ
SYNCB
§ DEPENDS ON PREVIOUS STATE AND DIVIDE RATIO
MIN 5ns
Figure 18. Clock Input Equivalent Circuit
Figure 21. SYNCB Timing with No Clock Present
SYNCHRONIZATION
Power-On SYNC
The outputs of the AD9513 can be synchronized by using the
SYNCB pin. Synchronization aligns the phases of the clock
outputs, respecting any phase offset that has been set on an
output’s divider.
A power-on sync (POS) is issued when the VS power supply is
turned on to ensure that the outputs start in synchronization.
The power-on sync works only if the VS power supply transi-
tions the region from 2.2 V to 3.1 V within 35 ms. The POS can
occur up to 65 ms after VS crosses 2.2 V. Only outputs which are
not divide = 1 are synchronized.
SYNCB
Figure 22. SYNCB Equivalent Input Circuit
Rev. 0 | Page 17 of 28
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