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AD9220ARS 参数 Datasheet PDF下载

AD9220ARS图片预览
型号: AD9220ARS
PDF下载: 下载PDF文件 查看货源
内容描述: 完整的12位1.5 / 3.0 / 10.0 MSPS单片A / D转换器 [Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters]
分类和应用: 转换器
文件页数/大小: 28 页 / 353 K
品牌: ADI [ ADI ]
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AD9221/AD9223/AD9220  
The calibration procedure consists of a two step process. First,  
the bipolar offset is calibrated by selecting CH2, the 2.5 V sys-  
tem reference, of the analog multiplexer and preloading the  
DAC, U5, with a midscale code of 1000 0000. If possible, sev-  
eral readings of the A/D should be taken and averaged to deter-  
mine the required digital offset adjustment code, U5. This  
averaged offset code requires an extra bit of resolution since 1  
LSB of U5 equates to 1/2 LSB of the AD9221/AD9223/AD9220.  
The required offset correction code to U5 can then be deter-  
mined. Second, the system gain is calibrated by selecting CH2,  
a 1.25 V input which corresponds to –FS of the A/D. Before the  
value is read, U4 should be preloaded with a code of 00 (Hex).  
Several readings can also be taken and averaged to determine  
the digital gain adjustment code to U2A. In this case, 1 LSB of  
the A/D corresponds to 1 LSB of U4.  
Referring to Figure 61, the AD9221/AD9223/AD9220 is config-  
ured for single-ended operation with a 2.5 V p-p input span and  
a 2.5 V common-mode voltage using an external, precision 2.5  
voltage reference, U1. This configuration and input span allows  
the buffer amplifier, U4, to be single supply. Also, it simplifies  
the design of the low temperature drift autocalibration circuitry  
which uses thin-film resistors for temperature stability and ratio-  
metric accuracy. The input of the AD9221/AD9223/AD9220  
can be easily configured for a wider span but it should remain  
within the input/output swing capabilities of a high speed, rail-  
to-rail, single-supply amplifier, U4 (e.g., AD8041).  
The gain and offset calibration circuitry is based on two 8-bit,  
current-output DAC08s, U3 and U5. The gain calibration  
circuitry consisting of U3, and an op amp, U2A, is configured  
to provide a low drift nominal 1.25 V reference to the AD9221/  
AD9223/AD9220. The resistor values which set the gain cali-  
bration range were selected to provide a nominal adjustment  
span of ±128 LSBs with 1 LSB resolution with respect to the  
A/D. Note that the bandwidth of the reference is low and, as a  
result, it is not possible to change the reference voltage rapidly  
in this mode.  
Due to the AD9221/AD9223/AD9220’s excellent INL perfor-  
mance, a two-point calibration procedure (i.e., –FS to midscale)  
instead of an endpoint calibration procedure was chosen. Also,  
since the bipolar offset is insensitive to any gain adjustment (due  
to the differential SHA of the A/D), an iterative calibration  
process is not required. The temperature stability of the circuit  
is enhanced by selecting a dual precision op amp for U2 (e.g.,  
OP293) and low temperature drift, thin film resistors. Note  
that this application circuit was not built at the release of this  
data sheet. Please consult Analog Devices for application assis-  
tance or comments.  
The offset calibration circuitry consists of a DAC, U5 and the  
buffer amplifier, U4. The DAC is configured for a bipolar ad-  
justment span of ±64 LSB with a 1/2 LSB resolution span with  
respect to the AD9221/AD9223/AD9220. Note that both cur-  
rent outputs of U5 were configured to provide a bipolar adjust-  
ment span. Also, RC is used to decouple the output of both  
DACs, U3 and U5, from their respective op amps.  
0.1F  
1.25k⍀  
1.25V  
162⍀  
2.5k⍀  
U2B  
2.5k⍀  
0.1F  
1.25V  
؎39mV  
U2A  
2.5k⍀  
0.1F  
2.5k⍀  
1.1k⍀  
U1  
2 
؋
 39⍀  
REF43  
0.1F  
10F  
CH1  
CH2  
CH3  
CH4  
CH5  
CH6  
CH7  
CH8  
+5V  
SENSE  
VREF  
R
100⍀  
2.5k⍀  
C
IOUT  
VREF(+)  
VREF(–)  
OUT  
U6  
ADG608  
U3  
DAC08  
AD9221/  
AD9223/  
AD9220  
IOUT  
BIT 1 – BIT 12  
OTR  
2.5k⍀  
39⍀  
VINA  
U4  
39⍀  
2.50V  
VINB  
R
100⍀  
R
C
100⍀  
C
2.5k⍀  
VREF(+)  
VREF(–)  
IOUT  
U5  
DAC08  
IOUT  
2.5k⍀  
Figure 61. Typical Multichannel Data Acquisition System  
–23–  
REV. D  
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