AD9221/AD9223/AD9220
clock is generated from another type of source (by gating, divid-
ing, or other method), it should be retimed by the original clock
at the last step.
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
Most of the power dissipated by the AD9221/AD9223/AD9220
is from the analog power supplies. However, lower clock speeds
will reduce digital current slightly. Figure 55 shows the relation-
ship between power and clock rate for each A/D.
1. The minimization of the loop area encompassed by a signal
and its return path.
66
2. The minimization of the impedance associated with ground
and power paths.
64
62
3. The inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
60
5V p-p
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.
58
2V p-p
56
54
52
50
It is important to design a layout that prevents noise from coupling
onto the input signal. Digital signals should not be run in paral-
lel with input signal traces and should be routed away from the
input circuitry. While the AD9221/AD9223/AD9220 features
separate analog and digital ground pins, it should be treated as
an analog component. The AVSS and DVSS pins must be joined
together directly under the AD9221/AD9223/AD9220. A solid
ground plane under the A/D is acceptable if the power and
ground return currents are managed carefully. Alternatively, the
ground plane under the A/D may contain serrations to steer
currents in predictable directions where cross-coupling between
analog and digital would otherwise be unavoidable. The
AD9221/AD9223/AD9220/EB ground layout, shown in Figure
65, depicts the serrated type of arrangement. The analog and
digital grounds are connected by a jumper below the A/D.
48
0.5
1.0
1.5
2.0
2.5
3.0
CLOCK FREQUENCY – MHz
Figure 55a. AD9221 Power Consumption vs. Clock
Frequency
125
120
115
110
Analog and Digital Supply Decoupling
5V p-p
105
The AD9221/AD9223/AD9220 features separate analog and
digital supply and ground pins, helping to minimize digital
corruption of sensitive analog signals. In general, AVDD, the
analog supply, should be decoupled to AVSS, the analog com-
mon, as close to the chip as physically possible. Figure 56
shows the recommended decoupling for the analog supplies;
0.1 µF ceramic chip capacitors should provide adequately low
impedance over a wide frequency range. Note that the AVDD
and AVSS pins are co-located on the AD9221/AD9223/AD9220
to simplify the layout of the decoupling capacitors and provide
the shortest possible PCB trace lengths. The AD9221/AD9223/
AD9220/EB power plane layout, shown in Figure 66 depicts a
typical arrangement using a multilayer PCB.
2V p-p
100
95
90
0
1
2
3
4
5
6
CLOCK FREQUENCY – MHz
Figure 55b. AD9223 Power Consumption vs. Clock
Frequency
300
280
26
INPUT = 5V p-p
AVDD
AD9221/
AD9223/
AD9220
0.1F
260
25
AVSS
INPUT = 2V p-p
240
15 AVDD
16 AVSS
0.1F
220
200
Figure 56. Analog Supply Decoupling
0
2
4
6
8
10
12
14
The CML is an internal analog bias point used internally by the
AD9221/AD9223/AD9220. This pin must be decoupled with
at least a 0.1 µF capacitor as shown in Figure 57. The dc level of
CLOCK FREQUENCY – MHz
Figure 55c. AD9220 Power Consumption vs. Clock
Frequency
–21–
REV. D
ADI [ ADI ]
