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AD9201ARS 参数 Datasheet PDF下载

AD9201ARS图片预览
型号: AD9201ARS
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道, 20 MHz的10位分辨率的CMOS ADC [Dual Channel, 20 MHz 10-Bit Resolution CMOS ADC]
分类和应用:
文件页数/大小: 20 页 / 434 K
品牌: AD [ ANALOG DEVICES ]
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AD9201
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
Parameter
With
Respect
to
P
in
Min
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–1.0
–0.3
–0.3
–0.3
–65
Max
+6.5
+6.5
+0.3
+6.5
AVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
+150
+150
+300
Units
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
No.
1
2
3
4
5
6
7
8
9
10
11
12
Name
DVSS
DVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Description
Digital Ground
Digital Supply
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9 (MSB)
AVDD
AVSS
DVDD
DVSS
AVSS
DVSS
AVDD
DVDD
CLK
AVSS
Digital Outputs
DVSS
AINA, AINB
AVSS
VREF
AVSS
REFSENSE
AVSS
REFT, REFB
AVSS
Junction Temperature
Storage Temperature
Lead Temperature
10 sec
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SELECT
CLOCK
SLEEP
INA-I
INB-I
REFT-I
REFB-I
AVSS
REFSENSE
VREF
AVDD
REFB-Q
REFT-Q
INB-Q
INA-Q
CHIP-SELECT
Hi I Channel Out, Lo Q Channel Out
Clock
Hi Power Down, Lo Normal Operation
I Channel, A Input
I Channel, B Input
Top Reference Decoupling, I Channel
Bottom Reference Decoupling, I Channel
Analog Ground
Reference Select
Internal Reference Output
Analog Supply
Bottom Reference Decoupling, Q Channel
Top Reference Decoupling, Q Channel
Q Channel, B Input
Q Channel, A Input
Hi-High Impedance, Lo-Normal Operation
ORDERING GUIDE
Temperature
Range
–40°C to +85°C
Package
Description
Package
Options*
Model
AD9201ARS
AD9201-EVAL
28-Lead SSOP
RS-28
Evaluation Board
*RS = Shrink Small Outline.
PIN CONFIGURATION
DVSS
DVDD
(LSB) D0
D1
D2
D3
D4
D5
D6
D7
D8
(MSB) D9
SELECT
CLOCK
CHIP-SELECT
INA-Q
INB-Q
REFT-Q
AD9201
TOP VIEW
(Not to Scale)
REFB-Q
AVDD
VREF
REFSENSE
AVSS
REFB-I
REFT-I
INB-I
INA-I
SLEEP
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” The
point used as “zero” occurs 1/2 LSB before the first code tran-
sition. “Full scale” is defined as a level 1 1/2 LSBs beyond the
last code transition. The deviation is measured from the center
of each particular code to the true straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9201 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. D