AD9201
REFERENCE AND REFERENCE BUFFER
The reference and buffer circuitry on the AD9201 is configured
for maximum convenience and flexibility. An illustration of the
equivalent reference circuit is show in Figure 26. The user can
select from five different reference modes through appropriate
pin-strapping (see Table I below). These pin strapping options
cause the internal circuitry to reconfigure itself for the appropri-
ate operating mode.
Table I. Table of Modes
Externally Set Voltage Mode (Figure 24)—this
mode uses
the on-chip reference, but scales the exact reference level though
the use of an external resistor divider network. VREF is wired to
the top of the network, with the REFSENSE wired to the tap
point in the resistor divider. The reference level (and input full
scale) will be equal to 1 V
×
(R1 + R2)/R1. This method can be
used for voltage levels from 0.7 V to 2.5 V.
1 F
0.1 F
+
5k
–
R2
R1
AVSS
VREF = 1 + R2
R1
I OR QREFT
0.1 F
10 F
0.1 F
REFSENSE
0.1 F
VREF
1V
+–
Mode
1V
2V
Programmable
External
Input Span
1V
2V
1 + (R1/R2)
= External Ref
REFSENSE Pin Figure
VREF
AGND
See Figure
AVDD
22
23
24
25
1 V Mode (Figure 22)—provides
a 1 V reference and 1 V input
full scale. Recommended for applications wishing to optimize
high frequency performance, or any circuit on a supply voltage
of less than 4 V. The part is placed in this mode by shorting the
REFSENSE pin to the VREF pin.
1V
0V
IINA
5k
IINB
10 F
0.1 F
5k
1V
QINB
QINA
1V
0V
AD9201
I OR QREFB
Figure 24. Programmable Reference
External Reference Mode (Figure 25)—in
this mode, the on-
chip reference is disabled, and an external reference is applied to
the VREF pin. This mode is achieved by tying the REFSENSE
pin to AVDD.
1V
0V
1V
0V
IINA
5k
IINB
QINB
QINA
AD9201
VREF
REFSENSE
I OR QREFT
0.1 F
0.1 F
I OR QREFB
0.1 F
10 F
10 F
1V
EXT
REFERENCE
10 F
0.1 F
AD9201
VREF
I OR QREFT
0.1 F
0.1 F
I OR QREFB
10 F
0.1 F
10 F
0.1 F
0.1 F
Figure 22. 0 V to 1 V Input
AVDD
REFSENSE
2 V Mode (Figure 23)—provides
a 2 V reference and 2 V input
full scale. Recommended for noise sensitive applications on 5 V
supplies. The part is placed in 2 V reference mode by grounding
(shorting to AVSS) the REFSENSE pin.
2V
0V
IINA
5k
IINB
10 F
0.1 F
5k
QINB
QINA
2V
0V
Figure 25. External Reference
AD9201
VREF
I OR QREFT
0.1 F
0.1 F
I OR QREFB
REFSENSE
0.1 F
10 F
Reference Buffer—The
reference buffer structure takes the
voltage on the VREF pin and level-shifts and buffers it for use
by various subblocks within the two A/D converters. The two
converters share the same reference buffer amplifier to maintain
the best possible gain match between the two converters. In the
interests of minimizing high frequency crosstalk, the buffered
references for the two converters are separately decoupled on
the IREFB, IREFT, QREFB and QREFT pins, as illustrated in
Figure 26.
10 F
0.1 F
Figure 23. 0 V to 2 V Input
–10–
REV. D
AD [ ANALOG DEVICES ]
