AD9066
CLOCK
LOCAL
OSCILLATOR
–16dBM
10
VMID
+
RF INPUT
(ANTENNA)
0
BANDPASS
FILTER
330
330
100nF
10
4.7 F
100nF
+
OPTIONAL
BPF
OR LPF
PLL
90
11
V
INB
6
1
CLKIN
28
27
26
25
24
23
V
INA
A OUTPUTS
(INPHASE)
AD9066
20
19
18
17
16
15
B OUTPUTS
(QUADRATURE)
MIDPOINT
BIAS
GENERATOR
AGC VOLTAGE
AGC
DETECTOR
RECEIVED SIGNAL
STRENGTH INDICATOR
PTAT
VOLTAGE
AD607
BIAS
CIRCUIT
Figure 8. Digitizer with AD607 Receiver Circuit
Theory of Operation
The AD9066 dual ADC employs a patented interpolated flash
architecture. This architecture enables 64 possible quantization
levels with only 32 comparator preamplifiers. This keeps input
capacitance to a minimum. The midpoint of the reference lad-
der is fed back to the analog input, allowing easy biasing of the
ADC to midscale for ac coupled applications.
As shown in Figure 4d, a simple resistor is used to provide the
reference ladder midpoint to the analog input. The high imped-
ance MOS inputs of the comparators insure no static voltage
drop across the resistor. This eliminates the need for an active
buffer (and its inherent offsets) to set the reference midpoint at
the analog input.
The outputs of the comparators are converted to a 6-bit word
and converted to CMOS levels. The digital signals are latched at
six stages (two pipeline delays) in the signal path. The digital
outputs are CMOS with approximately equal rise and fall times.
The encode clock utilizes a CMOS input stage with TTL-
compatible (1.4 V) thresholds. Internal clock buffers minimize
external clock drive requirements.
–6–
REV. A
AD [ ANALOG DEVICES ]
