AD9066–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(+V = +5 V, AIN = 15.5 MHz, Encode Rate = 60 MSPS, T
S
C
= T
A
)
Unit
mV
mV
V
LSBs
pF
kΩ
MHz
dB
LSBs
LSBs
Parameter
ANALOG INPUT
Full-Scale Input Range
Gain Matching (FS Range)
DC Input (Midscale)
1
Input Offset
1
Input Capacitance
Input Resistance (DC)
Input Bandwidth (3 dB)
Gain Flatness (to 15 MHz)
Integral Linearity
Differential Linearity
Monotonicity
SWITCHING PERFORMANCE
Max Conversion Rate
Output Delay (t
V
)
2
Output Delay (t
PD
)
2
Aperture Uncertainty (Jitter)
Aperture Time (t
A
)
DYNAMIC PERFORMANCE
3
Effective Number of Bits
SINAD
Harmonic Distortion (THD)
Crosstalk Rejection
ENCODE INPUT
Logic High Voltage
Logic Low Voltage
Input High Current
Input Low Current
Pulsewidth High
Pulsewidth Low
DIGITAL OUTPUTS
Output Coding
Logic High Voltage (I
OH
= 1 mA)
Logic Low Voltage (I
OL
= 1 mA)
POWER SUPPLY
+V
S
Supply Voltage
Power Supply Rejection Ratio
1
+V
S
Supply Current
Power Dissipation
4
Test
Level
VI
IV
V
VI
IV
VI
V
V
VI
VI
VI
VI
IV
IV
V
V
VI
VI
VI
IV
VI
VI
VI
VI
IV
IV
Temp
Full
Full
+25°C
Full
Full
Full
+25°C
+25°C
Full
Full
Full
Full
Full
Full
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9066JR
Min
Typ
475
500
+V
S
– 1.1
–1.0
25
10
45
100
0.25
Max
525
16
+1.0
15
55
AD9066AR/ARS
Min
Typ
Max
450
500
+V
S
– 1.1
–1.0
22
10
45
100
0.25
+1.0
15
57
530
16
–1.0
–0.5
Guaranteed
60
4
+1.0
+0.5
–1.0
–0.5
Guaranteed
60
4
+1.0
+0.5
11
10
1.0
5.3
34
40
40
2.0
0.8
500
500
7.0
7.0
Offset Binary
3.8
0.4
4.75
110
80
400
5.25
130
120
600
4.75
110
80
400
3.8
7.0
7.0
Offset Binary
5.7
36
50
50
5.2
33
40
40
2.0
10
1.0
5.7
36
50
50
12
MSPS
ns
ns
ps rms
ns
Bits
dB
dB
dBc
V
V
µA
µA
ns
ns
0.8
500
500
VI
VI
VI
IV
VI
VI
0.4
5.25
130
120
600
V
V
V
mV/V
mA
mW
NOTES
1
For ac coupled applications, the ADC is internally biased to insure that the midpoint transition of the ADC is within the limits specified with no signal applied. For
dc coupled applications, the dc value of the midpoint transition voltage will track the supply voltage within the limits shown for dc input (midscale) plus the dc offset.
Power Supply Rejection Ratio (PSRR) refers to the variation of the input signal range (gain) to supply voltage.
2
t
V
and t
PD
are measured from the 1.4 V level of the Clock and the 50% level between V
OH
and V
OL
. The ac load on all the digital outputs during test is 10 pF (max),
the dc load will not exceed
±
40
µA.
3
Effective number of bits (ENOB) and THD are measured using a FFT with a pure sine wave analog input @ 15.5 MHz, 1 dB below full scale. ENOB is calculated by
ENOB = (SNR – 1.76 dB)/6.02; THD is measured from full scale to the sum of the second through seventh harmonic of the input.
4
Typical thermal impedance for the “R” style (SOIC) 28-lead package is:
θ
JC
= 4°C/W,
θ
CA
= 41°C/W,
θ
JA
= 45°C/W, and the “RS” style (SSOP) 28-lead package is:
θ
JC
= 26.97°C/W,
θ
CA
= 51.61°C/W,
θ
JA
= 78.58°C/W.
Specifications subject to change without notice.
–2–
REV. A
AD [ ANALOG DEVICES ]
