AD9042
Equation 1:
linearity to appear as if it were random. T hen, the average
linearity over the range of dither will dominate SFDR
performance. In the AD9042, the repetitive cycle is every
15.625 mV p-p.
1/2
2
2
VNOISE rms
2
)
1+ε
212
SNR = –20 log 2 πF
tJ rms
+
+
(
ANALOG
212
T o insure adequate randomization, 5.3 mV rms is required;
this equates to a total dither power of –32.5 dBm. T his will
randomize the DNL errors over the complete range of the
residue converter. Although lower levels of dither such as that
from previous analog stages will reduce some of the linearity
errors, the full effect will only be gained with this larger dither.
Increasing dither even more may be used to reduce some of the
global INL errors. However, signals much larger than the mVs
proposed here begin to reduce the usable dynamic range of the
converter.
FANALOG = analog input frequency
t
= rms jitter of the encode (rms sum of encode source
and internal encode circuitry)
J
rms
ε
= average DNL of the ADC
VNOISE rms = V rms thermal noise referred to the analog input of
the ADC
P r ocessing Gain
Processing gain is the improvement in signal-to-noise ratio
(SNR) gained through DSP processes. Most of this processing
gain is accomplished using the channelizer chips. T hese special
purpose DSP chips not only provide channel selection and
filtering but also provide a data rate reduction. Few, if any,
general purpose DSPs can accept and process data at
40.96 MSPS. T he required rate reduction is accomplished
through a process called decimation. T he term decimation rate
is used to indicate the ratio of input data rate to output data
rate. For example, if the input data rate is 40.96 MSPS and the
output data rate is 30 kSPS, then the decimation rate is 1365.
Even with the 5.3 mV rms of noise suggested, SNR would be
limited to 36 dB if injected as broadband noise. T o avoid this
problem, noise may be injected as an out-of-band signal. Typically,
this may be around dc but may just as well be at FS/2 or at
some other frequency not used by the receiver. T he bandwidth
of the noise is several hundred kilohertz. By band-limiting and
controlling its location in frequency, large levels of dither may
be introduced into the receiver without seriously disrupting
receiver performance. T he result can be a marked improvement
in the SFDR of the data converter.
Figure 23 shows the same converter shown earlier but with this
injection of dither (ref. Figure 20). Spurious-free dynamic
range is now 94 dBFS. Figure 21 and 24 show an SFDR sweep
before and after adding dither.
Large processing gains may be achieved in the decimation and
filtering process. T he purpose of the channelizer, beyond
tuning, is to provide the narrowband filtering and selectivity that
traditionally has been provided by the ceramic or crystal filters
of a narrowband receiver. T his narrowband filtering is the
source of the processing gain associated with a wideband
receiver and is simply the ratio of the passband to whole band
expressed in dB. For example, if a 30 kHz AMPS signal is
being digitized with an AD9042 sampling at 40.96 MSPS, the
ratio would be 0.030 MHz/20.48 MHz. Expressed in log form,
the processing gain is –10 × log (0.030 MHz / 20.48 MHz) or
28.3 dB!
T o more fully appreciate the improvement that dither can have
on performance, Figures 22 and 25 show a before-and-after
dither using additional data samples in the Fourier transform.
Increasing to 128k sample points lowers the noise floor of the
FFT ; this simply makes it easier to “see” the dramatic reduction
in spurious levels resulting from dither.
+15V
LOW CONTROL
(0–1 VOLT)
Additional filtering and noise reduction techniques can be
achieved through DSP techniques; many applications do use
additional process gains through proprietary noise reduction
algorithms.
16kΩ
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1µF
A
NC202
NOISE
DIODE
2.2kΩ
+5V
(NoiseCom)
2kΩ
REF
A
O ver com ing Static Nonlinear ities with D ither
–5V
1kΩ
T ypically, high resolution data converters use multistage
techniques to achieve high bit resolution without large
comparator arrays that would be required if traditional “flash”
ADC techniques were employed. T he multistage converter
typically provides better wafer yields meaning lower cost and
much lower power. However, since it is a multistage device,
certain portions of the circuit are used repetitively as the analog
input sweeps from one end of the converter range to the other.
Although the worst DNL error may be less than an LSB, the
repetitive nature of the transfer function can play havoc with low
level dynamic signals. Spurious signals for a full-scale input
may be –88 dBc, however 29 dB below full scale, these repeti-
tive DNL errors may cause spurious-free dynamic range (SFDR)
to fall to 80 dBc as shown in Figure 20.
OP27
0.1µF
AD600
OPTIONAL HIGH
POWER DRIVE
CIRCUIT
39Ω
390Ω
Figure 53. Noise Source (Dither Generator)
T he simplest method for generating dither is through the use of
a noise diode (Figure 53). In this circuit, the noise diode
NC202 generates the reference noise that is gained up and
driven by the AD600 and OP27 amplifier chain. T he level of
noise may be controlled by either presetting the control voltage
when the system is set up, or by using a digital-to-analog
converter (DAC) to adjust the noise level based on input signal
conditions. Once generated, the signal must be introduced to
the receiver strip. T he easiest method is to inject the signal into
the drive chain after the last down conversion as shown in
Figure 54.
A common technique for randomizing and reducing the effects
of repetitive static linearity is through the use of dither. T he
purpose of dither is to force the repetitive nature of static
REV. A
–21–
ADI [ ADI ]
