AD9042
+5V (A)
+5V (D)
499Ω
CHANNELIZER
(REF. FIG 51)
CMOS
BUFFER
PRESELECT
FILTER
ADSP-2181
5–15MHz
PASSBAND
LNA
D11
AIN
I & Q
DATA
LO
DRIVE
12
NETWORK
CONTROLLER
INTERFACE
AD9042
864MHz
ENCODE
ENCODE
M/N PLL
SYNTHESIZER
REF
IN
CLK
D0
40.96MHz
REFERENCE
CLOCK
Figure 52. Sim plified 5 MHz Wideband “A” Carrier Receiver
System Requir em ents
Another option can be found through bandpass sampling. If the
analog input signal range is from dc to FS/2, then the amplifier
and filter combination must perform to the specification
required. However, if the signal is placed in the third Nyquist
zone (FS to 3 FS/2), the amplifier is no longer required to meet
the harmonic performance required by the system specifications
since all harmonics would fall outside the passband filter. For
example, the passband filter would range from FS to 3 FS/2.
T he second harmonic would span from 2 FS to 3 FS, well
outside the passband filter’s range. T he burden then has been
passed off to the filter design provided that the ADC meets the
basic specifications at the frequency of interest. In many
applications, this is a worthwhile tradeoff since many complex
filters can easily be realized using SAW and LCR techniques
alike at these relatively high IF frequencies. Although harmonic
performance of the drive amplifier is relaxed by this technique,
intermodulation performance cannot be sacrificed since
intermods must be assumed to fall in-band for both amplifiers
and converters.
Figure 52 shows a typical wideband receiver subsystem based
around the AD9042. T his strip consists of a wideband IF filter,
amplifier, ADC, latches, channelizer and interface to a digital
signal processor. T his design shows a typical clocking scheme
used in many receiver designs. All timing within the system is
referenced back to a single clock. While this is not necessary, it
does facilitate PLL design, ease of manufacturing, system test,
and calibration. Keeping in mind that the overall performance
goal is to maintain the best possible dynamic range, many
considerations must be made.
One of the biggest challenges is selecting the amplifier used to
drive the AD9042. Since this is a communications application,
the key specification for this amplifier is spurious-free dynamic
range, or SFDR. An amplifier should be selected that can
provide SFDR performance better than 80 dB into 250 ohms.
One such amplifier is the AD9631. T hese low spurious levels
are necessary as harmonics due to the drive amplifier and ADC
could distort the desired signals of interest.
T wo other key considerations for the digital wideband receiver
are converter sample rate and IF frequency range. Since
performance of the AD9042 converter is nearly independent of
both sample rate and analog input frequency (Figures 11, 12,
and 17), the designer has greater flexibility in the selection of
these parameters. Also, since the AD9042 is a bipolar device,
power dissipation is not a function of sample rate. T hus there is
no penalty paid in power by operating at faster sample rates. All
of this is good, because by carefully selecting input frequency
range and sample rate, the drive amplifier and ADC harmonics
can actually be placed out-of-band. T hus other components
such as filters and IF amplifiers may actually end up being the
limiting factor on dynamic range.
Noise Floor and SNR
Oversampling is the act of sampling at a rate that is greater than
twice the bandwidth of the signal desired. Oversampling does
not have anything to do with the actual frequency of the
sampled signal, it is the bandwidth of the signal that is key.
Bandpass or “IF” sampling refers to sampling a frequency that
is higher than Nyquist and often provides additional benefits
such as down conversion using the ADC and track-and-hold as
a mixer. Oversampling leads to processing gains because the
faster the signal is digitized, the wider the distribution of noise.
Since the integrated noise must remain constant, the actual
noise floor is lowered by 3 dB each time the sample rate is
doubled. T he effective noise density for an ADC may be
calculated by the equation:
For example, if the system has second and third harmonics that
are unacceptably high, by carefully selecting the encode rate and
signal bandwidth, these second and third harmonics can be
placed out-of-band. For the case of an encode rate equal to
40.96 MSPS and a signal bandwidth of 5.12 MHz, placing the
fundamental at 5.12 MHz places the second and third harmon-
ics out of band as shown in the table below.
10−SNR /20
VNOISE rms
/ Hz =
4 FS
For a typical SNR of 68 dB and a sample rate of 40.96 MSPS,
this is equivalent to . T his equation shows the
31 nV / Hz
relationship between SNR of the converter and the sample rate
FS. T his equation may be used for computational purposes to
determine overall receiver noise.
Table III.
Encode Rate
Fundamental
Second Harmonic 10.24 MHz–20.48 MHz
T hird Harmonic 15.36 MHz–10.24 MHz
40.96 MSPS
5.12 MHz–10.24 MHz
T he signal-to-noise ratio (SNR) for an ADC can be predicted.
When normalized to ADC codes, the following equation
accurately predicts the SNR based on three terms. T hese are
jitter, average DNL error and thermal noise. Each of these
terms contributes to the noise within the converter.
REV. A
–20–
ADI [ ADI ]
