欢迎访问ic37.com |
会员登录 免费注册
发布采购

AD8362ARUZ-REEL7 参数 Datasheet PDF下载

AD8362ARUZ-REEL7图片预览
型号: AD8362ARUZ-REEL7
PDF下载: 下载PDF文件 查看货源
内容描述: 50 Hz至3.8 GHz的65分贝TruPwr ?探测器 [50 Hz to 3.8 GHz 65 dB TruPwr? Detector]
分类和应用: 模拟IC信号电路光电二极管
文件页数/大小: 32 页 / 1029 K
品牌: ADI [ ADI ]
 浏览型号AD8362ARUZ-REEL7的Datasheet PDF文件第22页浏览型号AD8362ARUZ-REEL7的Datasheet PDF文件第23页浏览型号AD8362ARUZ-REEL7的Datasheet PDF文件第24页浏览型号AD8362ARUZ-REEL7的Datasheet PDF文件第25页浏览型号AD8362ARUZ-REEL7的Datasheet PDF文件第27页浏览型号AD8362ARUZ-REEL7的Datasheet PDF文件第28页浏览型号AD8362ARUZ-REEL7的Datasheet PDF文件第29页浏览型号AD8362ARUZ-REEL7的Datasheet PDF文件第30页  
AD8362  
To operate in controller mode, the link between VSET and  
VOUT is broken. A setpoint voltage is applied to the VSET  
input, while VOUT is connected to the gain control terminal  
of the VGA, and the AD8362 RF input is connected to the out-  
put of the VGA (generally using a directional coupler or power  
splitter and some additional attenuation). Based on the defined  
relationship between VOUT and the RF input signal when the  
device is in measurement mode, the AD8362 adjusts the voltage  
on VOUT (VOUT is now an error amplifier output) until the  
level at the RF input corresponds to the applied VSET. For  
example, in a closed loop system, if VSET is set to 3 V, VOUT  
increases or decreases until the input signal is equal to 0 dBm.  
This relationship follows directly from the measurement mode  
transfer function (see Figure 10, Figure 11, and Figure 12).  
Therefore, when the AD8362 operates in controller mode, there  
is no defined relationship between VSET and VOUT. VOUT  
settles to a value that results in balance between the input signal  
levels appearing at INHI/INLO and VSET.  
OPERATION IN CONTROLLER MODE  
The AD8362 provides a controller mode feature at the VOUT  
pin. Using VSET for the setpoint voltage, it is possible for the  
AD8362 to control subsystems such as power amplifiers (PAs),  
VGAs, or variable voltage attenuators (VVAs), which have  
output power that decreases monotonically with respect to  
their (increasing) gain control signal.  
CONTROLLED SYSTEM  
(OUTPUT POWER  
DECREASES AS  
VAPC INCREASES)  
P
P
OUTPUT  
INPUT  
OUT  
IN  
VAPC  
OUTPUT CONTROL VOLTAGE  
0.1V TO 4.9V  
V
S
AD8362  
ATTN  
1
2
3
4
5
6
7
8
COMM  
CHPF  
DECL  
INHI  
16  
15  
14  
13  
12  
11  
10  
9
ACOM  
VREF  
VTGT  
VPOS  
VOUT  
VSET  
ACOM  
CLPF  
C1  
C8  
1:4 Z-RATIO  
0.1µF  
1000pF  
C4  
1nF  
C6  
100pF  
C2  
1nF  
C10  
1000pF  
INLO  
C7  
1nF  
SETPOINT  
VOLTAGE  
INPUT  
C5  
For this output power control loop to be stable, a ground-  
referenced capacitor must be connected to the CLPF pin.  
This capacitor integrates the internal error current that is  
present when the loop is not balanced.  
DECL  
PWDN  
COMM  
100pF  
T1  
ETC1.6-4-2-3  
0V TO 3.5V  
C3  
(SEE TEXT)  
Figure 64. Basic Connections for Controller Mode Operation  
Increasing VSET, which corresponds to demanding a higher  
signal from the VGA, tends to decrease VOUT. The VGA or VVA  
therefore must have a negative sense. In other words, increasing  
the gain control voltage decreases gain. If this is not the case, an  
op amp, configured as an inverter with suitable level shifting, can  
be used to correct the sense of the VOUT signal.  
Rev. D | Page 26 of 32  
 
 复制成功!