AD8362
MAIN MODES OF OPERATION
V
S
Both measurement and controller modes are supported by the
AD8362. Typical connections for the measurement mode,
which may also be viewed as the rms voltmeter mode, are also
illustrated in Figure 48. The output, VOUT, is proportional to
the logarithm of the rms magnitude of the input signal (that is,
a linear-on-dB response). When used in an accurately known
system impedance (but only then), the output is a scaled decibel
measurement of the power represented by the input voltage.
+5V nom, @ 24mA
AD8362
NO CONNECTION
FOR f >10MHz
3.3Ω
1
2
3
4
5
6
7
8
COMM ACOM 16
NC
CHPF
DECL
INHI
VREF 15
VTGT 14
VPOS 13
VOUT 12
VSET 11
0.1µF
1nF
1nF
V
SIGNAL INPUT
Z = 2 × 100Ω
1mV – 1V rms
C
CPL
RAIL-TO-RAIL
OUT
INLO
DECL
CONTROL OUTPUT
SETPOINT INPUT
0V–3.5V
1nF
PWDN ACOM 10
COMM CLPF
The choice of the capacitances CCPL, CDEC, CHPF, and CLPF
depends on the lowest frequency to be included in the
measurement spectrum. The default values shown support
operation down to 100 Hz. Using a large enough value of CLPF
(10 µF) to ensure sufficient filtering at this low input frequency,
the response time is approximately 20 ms over most of the
dynamic range. In high frequency applications, this capacitor is
much smaller and is usually chosen to minimize the response
time, consistent with well-behaved, large-signal behavior. In this
figure, CHPF is also shown as 10 µF, to lower the high-pass
corner to about 90 Hz. However, no capacitor will be needed
here in most HF applications since the internally set high-pass
corner is at about 2 MHz.
THIS CONNECTION
SETS CHIP-ENABLE
9
300pF
Figure 49. Basic Controller Mode Connections
Controller mode operation is more closely analogous to that of
a classical proportional/integral/derivative (PID) loop. The
error corresponding to the decibel deviation from the setpoint
is integrated by current into a capacitor (the sum of the internal
and external capacitance CLPF) until such deviation is nulled.
This action provides the fundamental proportional part of the
loop response (although VOUT has decibel scaling). The Q of
this system can be adjusted to minimize the loop response time
by including a resistor in series with CLPF, generating a
transmission zero, which provides the derivative term of a
standard PID loop.
Comparing the controller mode illustrated in Figure 49, the
AD8362 is used here to monitor the output of a variable gain
(or variable output power) signal processing element, frequently
a power amplifier, and adjust its output to a desired target value
(the setpoint) under the control of VSET. In this mode, its
function is somewhat like an RF comparator. With the path
from VOUT to VSET broken, any input larger than the
corresponding setpoint causes VOUT to rail to its maximum
value (which might loosely be viewed as a logic high). For
inputs smaller than the setpoint, the controller’s output falls to a
near-ground level (logic low). Using the AD8362 simply as a
threshold detector, this viewpoint may be useful, but in most
applications, it is an oversimplification. The AD8362 invariably
operates with the control loop closed, either locally with VOUT
connected to VSET (as in measurement mode), or globally via
some external nonlinear element (as in controller mode).
As a simple example, assume that the AD8362 operates at an
input power level of −20 dBm re: 50 Ω. Connected in the
measurement mode, it generates a VOUT of 2.00 V, because this
input is +40 dB above the intercept at −60 dBm and is scaled to
50 mV/dB. Rearranged to the controller mode with exactly this
voltage now externally applied to the VSET pin, the loop forces
VOUT to the control voltage required by the gain element to
provide a power sample of −20 dBm.
Of course, any control loop of this sort operates correctly
only if VSET corresponds to a power level (or a small sample of
such) that can actually be provided by the external gain element.
When this is a power amplifier, including the required amount
of RF attenuation ensures this condition. In certain instrument-
ation situations, it may be necessary to provide some low noise
gain ahead of the AD8362’s input.
These two primary modes of use are discussed in more detail,
with emphasis on practical considerations.
Rev. B | Page 21 of 36
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