AD8362
USING THE AD8362
V
S
The AD8362 requires a single supply of nominally 5 V; its
performance is essentially unaffected by variations of up to
10%, the range over which the stated specifications apply.
Supplies as low as 2.7 V may be used with some loss of
performance at high inputs and at temperature extremes.
+5V nom, @ 24mA
AD8362
3.3Ω
1
2
3
4
COMM ACOM 16
CHPF
VREF 15
C
C
DEC
0.1µF
14
DECL
INHI
VTGT
DEC
1nF
V
VPOS 13
VOUT 12
SIGNAL INPUT
Z = 2 × 100Ω
The AD8362 is disabled by a logic high on the PWDN pin,
which may be directly grounded for continuous operation,
when the supply current at 27°C is nominally 24 mA and
essentially independent of supply voltage. When powered
down by a logic low on PWDN, the supply current is reduced
to about 275 µA.
C
CPL
5
6
INLO
DECL
1mV – 1V rms
OUT
11
VSET
C
DEC
LOGIC HIGH FOR
POWER-DOWN
7
8
PWDN ACOM 10
COMM CLPF
9
C
LPF
Figure 48. Basic Measurement Mode Connections
BASIC CONNECTIONS
The supply is connected to the VPOS pin using the decoupling
network shown in Figure 48, whose capacitors must provide a
low impedance over the full frequency range of the input, and
should be placed as close as possible to the VPOS pin. Two
different capacitors are used in parallel to reduce the overall
impedance since these have different resonant frequencies.
However, the measurement accuracy is not critically dependent
on supply decoupling because the high frequency signal path is
confined to the relevant input pins. It is more important that the
lead lengths to INHI and INLO, and in the decoupling
capacitors from both of the DECL pins to ground, and the
connections from COMM to the ground plane all use the
shortest possible connections.
Rev. B | Page 20 of 36
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