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AD8307ARZ 参数 Datasheet PDF下载

AD8307ARZ图片预览
型号: AD8307ARZ
PDF下载: 下载PDF文件 查看货源
内容描述: 低成本DC - 500 MHz的92分贝对数放大器 [Low Cost DC-500 MHz, 92 dB Logarithmic Amplifier]
分类和应用: 模拟计算功能信号电路放大器光电二极管PC
文件页数/大小: 24 页 / 510 K
品牌: ADI [ ADI ]
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AD8307  
7
VPS  
transient input voltage that can block the lower reaches of the  
dynamic range until it has become much less than the signal.  
125  
125Ω  
INPUT  
STAGE  
MAIN GAIN  
STAGES  
TO LAST  
DETECTOR  
In most applications, the signal is single sided and can be  
applied to either Pin 1 or Pin 8, with the other pin ac-coupled to  
ground. Under these conditions, the largest input signal that  
can be handled by the AD8307 is 10 dBm (sine amplitude of  
1 V) when operating from a 3 V supply; 1ꢀ dBm can be  
handled using a 5 V supply. The full 1ꢀ dBm can be achieved for  
supplies down to 2.7 V, using a fully balanced drive. For  
frequencies above about 10 MHz, this is most easily achieved  
using a matching network. Using such a network, having an  
inductor at the input, the input transient is eliminated.  
Occasionally, it is desirable to use the dc-coupled potential of  
the AD8307. The main challenge here is to present signals to  
the log amp at the elevated common-mode input level,  
requiring the use of low noise, low offset buffer amplifiers.  
Using dual supplies of 3 V, the input pins can operate at  
ground potential.  
Q1  
64µA AT  
S
BALANCE  
Q2  
gm  
AVERAGE  
ERROR  
OFS  
3
BIAS, ~1.2V  
CURRENT  
Q3  
36kΩ  
Q4  
C
C
HP  
OFS  
48kΩ  
2
COM  
Figure 30. Offset Interface and Offset Nulling Path  
The offset feedback is limited to a range of 1.ꢀ mV; signals larger  
than this override the offset control loop, which only affects  
performance for very small inputs. An external capacitor reduces  
the high-pass corner to arbitrarily low frequencies; using 1 μF this  
corner is below 10 Hz. All ADI log amps use an offset nulling loop;  
the AD8307 differs in using this single sided form.  
OUTPUT INTERFACE  
OFFSET INTERFACE  
The outputs from the nine detectors are differential currents,  
having an average value that is dependent on the signal input  
level, plus a fluctuation at twice the input frequency. The  
currents are summed at nodes LGP and LGM in Figure 31.  
Further currents are added at these nodes, to position the  
intercept, by slightly raising the output for zero input, and to  
provide temperature compensation. Since the AD8307 is not  
laser trimmed, there is a small uncertainty in both the log slope  
and the log intercept. These scaling parameters can be adjusted.  
The input referred dc offsets in the signal path are nulled via the  
interface associated with Pin 3, shown in Figure 30. Q1 and Q2  
are the first stage input transistors, with their corresponding  
load resistors (125 Ω). Q3 and Q4 generate small currents,  
which can introduce a dc offset into the signal path. When the  
voltage on OFS is at about 1.5 V, these currents are equal, and  
nominally ꢀ4 μA. When OFS is taken to ground, Q4 is off and  
the effect of the current in Q3 is to generate an offset voltage of  
ꢀ4 μV × 125 Ω = 8 mV. Since the first stage gain is ×5, this is  
equivalent to a input offset (INP to INM) of 1.ꢀ mV. When OFS  
is taken to its most positive value, the input referred offset is  
reversed to −1.ꢀ mV. If true dc coupling is needed, down to very  
small inputs, this automatic loop must be disabled, and the  
residual offset eliminated using a manual adjustment.  
For zero signal conditions, all the detector output currents are  
equal. For a finite input of either polarity, their difference is  
converted by the output interface to a single sided unipolar  
current nominally scaled 2 μA/dB (40 μA/decade), at Pin OUT.  
An on-chip 12.5 kΩ resistor, R1, converts this current to a  
voltage of 25 mV/dB. C1 and C2 are effectively in shunt with R1  
and form a low-pass filter pole with a corner frequency of about  
5 MHz. The pulse response settles to within 1% of the final  
value within 300 ns. This integral low-pass filter provides  
adequate smoothing in many IF applications. At 10.7 MHz, the  
2f ripple is 12.5 mV in amplitude, equivalent to 0.5 dB, and  
only 0.5 mV ( 0.02 dB) at f = 50 MHz. A filter capacitor CFLT  
added from Pin OUT to ground lowers this corner frequency.  
Using 1 μF, the ripple is maintained to less than 0.5 dB down  
to input frequencies of 100 Hz. Note that COFS should also be  
increased in low frequency applications, and is typically made  
In normal operation, however, using an ac-coupled input signal,  
the OFS pin should be left open. Any residual input offset  
voltage is then automatically nulled by the action of the  
feedback loop. The gm cell, which is gated off when the chip is  
disabled, converts any output offset (sensed at a point near the  
end of the cascade of amplifiers) to a current. This is integrated  
by the on-chip capacitor CHP, and any added external  
capacitance COFS, so as to generate an error voltage, which is  
applied back to the input stage in the polarity needed to null the  
output offset. From a small signal perspective, this feedback  
alters the response of the amplifier, which, rather than behaving  
as a fully dc-coupled system, now exhibits a zero in its ac  
transfer function, resulting in a closed loop high-pass corner at  
about 1.5 MHz.  
equal to CFLT  
.
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