AD8307
INTERFACES
The AD8307 comprises six main amplifier/limiter stages, each
having a gain of 14.3 dB and small signal bandwidth of
900 MHz; the overall gain is 8ꢀ dB with a −3 dB bandwidth of
500 MHz. These six cells, and their associated gm styled full
wave detectors, handle the lower two-thirds of the dynamic
range. Three top end detectors, placed at 14.3 dB taps on a
passive attenuator, handle the upper third of the 90 dB range.
Biasing for these cells is provided by two references: one
determines their gain; the other is a band gap circuit that
determines the logarithmic slope and stabilizes it against supply
and temperature variations. The AD8307 can be enabled/
disabled by a CMOS-compatible level at ENB (Pin ꢀ). The first
amplifier stage provides a low voltage noise spectral density
(1.5 nV/√Hz).
tolerance is typically within 20%. Similarly, the capacitors have
a typical tolerance of 15% and essentially zero temperature or
voltage sensitivity. Most interfaces have additional small junction
capacitances associated with them, due to active devices or ESD
protection; these can be neither accurate nor stable. Component
numbering in each of these interface diagrams is local.
ENABLE INTERFACE
The chip enable interface is shown in Figure 28. The currents in
the diode-connected transistors control the turn on and turn off
states of the band gap reference and the bias generator, and are a
maximum of 100 μA when Pin ꢀ is taken to 5 V, under worst-
case conditions. Left unconnected, or at a voltage below 1 V, the
AD8307 is disabled and consume a sleep current of under 50 μA;
tied to the supply, or a voltage above 2 V, it is fully enabled. The
internal bias circuitry is very fast, typically <100 ns for either off
or on. In practice, the latency period before the log amp exhibits
its full dynamic range is more likely to be limited by factors
relating to the use of ac coupling at the input or the settling of
the offset control loop.
The differential current-mode outputs of the nine detectors are
summed and then converted to single sided form in the output
stage, nominally scaled 2 μA/dB. The logarithmic output
voltage is developed by applying this current to an on-chip
12.5 kΩ resistor, resulting in a logarithmic slope of 25 mV/dB
(that is, 500 mV/decade) at Pin OUT. This voltage is not
buffered, allowing the use of a variety of special output
interfaces, including the addition of post-demodulation
filtering. The last detector stage includes a modification to
temperature stabilize the log intercept, which is accurately
positioned to make optimal use of the full output voltage range
available. The intercept can be adjusted using the INT pin,
which adds or subtracts a small current to the signal current.
AD8307
40kΩ
6
ENB
TO BIAS
STAGES
2
COM
Figure 28. Enable Interface
7
VPS
AD8307
S
125Ω
125Ω
BAND GAP REFERENCE
7
6
5
VPS
7.5mA
ENB
INT
AND BIASING
6kΩ
COM
SIX 14.3dB 900MHz
AMPLIFIER STAGES
C
2kΩ
2kΩ
6kΩ
+INP
P
INP
INM
8
1
8
1
Q1
INP
INM
MIRROR
1.1kΩ
–INP
TOP-END
2µA
/dB
3
4kΩ
C
C
D
~3kΩ
DETECTORS
OUT
OFS
4
3
2
NINE DETECTOR CELLS
SPACED 14.3dB
Q2
12.5kΩ
COM
TYP 2.2V FOR
3V SUPPLY,
3.2V AT 5V
M
2
COM
I
E
INPUT-OFFSET
COMPENSATION LOOP
COM
2.4mA
S
2
Figure 27. Main Features of the AD8307
COM
The last gain stage also includes an offset sensing cell. This
generates a bipolarity output current when the main signal path
has an imbalance due to accumulated dc offsets. This current is
integrated by an on-chip capacitor (which can be increased in
value by an off-chip component at OFS). The resulting voltage
is used to null the offset at the output of the first stage. Since it
does not involve the signal input connections, whose ac-coupling
capacitors otherwise introduce a second pole in the feedback
path, the stability of the offset correction loop is assured.
Figure 29. Signal Input Interface
INPUT INTERFACE
Figure 29 shows the essentials of the signal input interface. CP
and CM are the parasitic capacitances to ground; CD is the
differential input capacitance, mostly due to Q1 and Q2. In
most applications, both input pins are ac-coupled. The switches
close when Enable is asserted. When disabled, the inputs float,
bias current IE is shut off, and the coupling capacitors remain
charged. If the log amp is disabled for long periods, small
leakage currents discharge these capacitors. If they are poorly
matched, charging currents at power-up can generate a
The AD8307 is built on an advanced, dielectrically isolated,
complementary bipolar process. Most resistors are thin film
types having a low temperature coefficient of resistance (TCR)
and high linearity under large signal conditions. Their absolute
Rev. C | Page ±4 of 24
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