Data Sheet
AD7904/AD7914/AD7924
TIMING SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
Parameter1 AVDD = 3 V
AVDD = 5 V
Unit
Description
2
fSCLK
10
10
kHz min
MHz max
20
20
tCONVERT
tQUIET
16 × tSCLK
50
16 × tSCLK
50
ns min
Minimum quiet time required between the CS rising edge and the start
of the next conversion
t2
10
10
ns min
ns max
ns max
ns min
ns min
ns min
CS to SCLK setup time
3
t3
35
30
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
3
t4
40
0.4 × tSCLK
0.4 × tSCLK
10
15/45
10
5
20
1
40
0.4 × tSCLK
0.4 × tSCLK
10
15/35
10
5
20
1
t5
t6
t7
t8
t9
t10
t11
t12
4
ns min/ns max SCLK falling edge to DOUT high impedance
ns min
ns min
ns min
μs max
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
16th SCLK falling edge to CS high
Power-up time from full shutdown/auto shutdown modes
1 Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V (see Figure 2).
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE
.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
I
OL
200µA
TO
OUTPUT
PIN
1.6V
C
L
50pF
I
OH
200µA
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. C | Page 9 of 32
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