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AD7914BRU-REEL 参数 Datasheet PDF下载

AD7914BRU-REEL图片预览
型号: AD7914BRU-REEL
PDF下载: 下载PDF文件 查看货源
内容描述: 4通道, 1 MSPS , 8位/ 10位/ 12位ADC,定序器采用16引脚TSSOP [4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP]
分类和应用: 转换器模数转换器光电二极管
文件页数/大小: 32 页 / 525 K
品牌: ADI [ ADI ]
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Data Sheet  
AD7904/AD7914/AD7924  
AD7924 SPECIFICATIONS  
AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.  
Table 3.  
Parameter  
B Version1  
Unit  
Test Conditions/Comments  
fIN = 50 kHz sine wave, fSCLK = 20 MHz  
@ 5 V, B models  
@ 5 V, W models  
@ 3 V, typically 69.5 dB  
B models  
DYNAMIC PERFORMANCE  
Signal to (Noise + Distortion) (SINAD)2  
70  
dB min  
dB min  
dB min  
dB min  
dB min  
dB max  
dB max  
dB max  
69.5  
69  
Signal-to-Noise Ratio (SNR)  
70  
69.5  
−77  
−73  
−78  
W models  
Total Harmonic Distortion (THD)2  
@ 5 V, typically −84 dB  
@ 3 V, typically −77 dB  
@ 5 V, typically −86 dB  
fa = 40.1 kHz, fb = 41.5 kHz  
Peak Harmonic or Spurious Noise (SFDR)  
Intermodulation Distortion (IMD)  
Second-Order Terms  
Third-Order Terms  
Aperture Delay  
−90  
−90  
10  
dB typ  
dB typ  
ns typ  
Aperture Jitter  
50  
ps typ  
Channel-to-Channel Isolation2  
Full Power Bandwidth  
−85  
8.2  
1.6  
dB typ  
MHz typ  
MHz typ  
fIN = 400 kHz  
@ 3 dB  
@ 0.1 dB  
DC ACCURACY  
Resolution  
12  
Bits  
Integral Nonlinearity (INL)2  
Differential Nonlinearity (DNL)2  
0 V to REFIN Input Range  
Offset Error2  
Offset Error Match2  
Gain Error2  
Gain Error Match2  
1
LSB max  
LSB max  
−0.9/+1.5  
Guaranteed no missed codes to 12 bits  
Straight binary output coding  
Typically 0.5 LSB  
8
LSB max  
LSB max  
LSB max  
LSB max  
0.5  
1.5  
0.5  
0 V to 2 × REFIN Input Range  
−REFIN to +REFIN biased about REFIN with twos  
complement output coding  
Positive Gain Error2  
Positive Gain Error Match2  
Zero Code Error2  
1.5  
0.5  
8
0.5  
1
LSB max  
LSB max  
LSB max  
LSB max  
LSB max  
LSB max  
Typically 0.8 LSB  
Zero Code Error Match2  
Negative Gain Error2  
Negative Gain Error Match2  
ANALOG INPUT  
0.5  
Input Voltage Range  
0 to REFIN  
V
RANGE bit set to 1  
0 to 2 × REFIN  
V
RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V  
DC Leakage Current  
Input Capacitance  
REFERENCE INPUT  
REFIN Input Voltage  
DC Leakage Current  
REFIN Input Impedance  
LOGIC INPUTS  
1
20  
μA max  
pF typ  
2.5  
1
36  
V
1% specified performance  
fSAMPLE = 1 MSPS  
μA max  
kΩ typ  
Input High Voltage, VINH  
Input Low Voltage, VINL  
Input Current, IIN  
0.7 × VDRIVE  
0.3 × VDRIVE  
1
10  
V min  
V max  
μA max  
pF max  
Typically 10 nA, VIN = 0 V or VDRIVE  
3
Input Capacitance, CIN  
Rev. C | Page 7 of 32  
 
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