AD7904/AD7914/AD7924
Data Sheet
Depending on the throughput rate selected, if the timer register
is loaded with a value such as 803 (803 + 1 = 804), then 100.5
SCLKs will occur between interrupts and subsequently between
transmit instructions. This setup results in nonequidistant
sampling because the transmit instruction occurs on an SCLK
edge. If the number of SCLKs between interrupts is a whole
integer value N, equidistant sampling is implemented by the DSP.
GROUNDING AND LAYOUT
The AD7904/AD7914/AD7924 have very good immunity to
noise on the power supplies (see Figure 6). However, care
should be taken with regard to grounding and layout.
The PCB that houses the AD7904/AD7914/AD7924 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes because it
provides the best shielding. All four AGND pins of the AD7904/
AD7914/AD7924 should be sunk in the AGND plane. Digital
and analog ground planes should be joined at only one place. If
the AD7904/AD7914/AD7924 are in a system where multiple
devices require an AGND-to-DGND connection, the connection
should still be made at one point only: a star ground point
established as close as possible to the AD7904/AD7914/AD7924.
AD7904/AD7914/AD7924 to DSP563xx
The connection diagram in Figure 32 shows how the AD7904/
AD7914/AD7924 can be connected to the ESSI (synchronous
serial interface) of the DSP563xx family of DSPs from Motorola.
Each ESSI (two on board) is operated in synchronous mode
(SYN bit in CRB = 1) with internally generated 1-bit clock
period frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 =
0 in CRB). Normal operation of the ESSI is selected by setting
MOD = 0 in the CRB. Set the word length to 16 by setting bits
WL1 = 1 and WL0 = 0 in CRA. The FSP bit in the CRB should
be set to 1 so that the frame sync is negative. Note that for signal
processing applications, it is imperative that the frame synchroni-
zation signal from the DSP563xx provide equidistant sampling.
Avoid running digital lines under the device because these lines
couple noise onto the die. The analog ground plane should be
allowed to run under the AD7904/AD7914/AD7924 to avoid
noise coupling. The power supply lines to the AD7904/AD7914/
AD7924 should use as large a trace as possible to provide low
impedance paths and reduce the effects of glitches on the power
supply line. Fast switching signals such as clocks should be
shielded with digital ground to avoid radiating noise to other
sections of the board, and clock signals should never be run
near the analog inputs. Avoid crossover of digital and analog
signals. Traces on opposite sides of the board should run at
right angles to each other to reduce the effects of feedthrough
through the board. A microstrip technique is by far the best, but
is not always possible with a double-sided board. In this
technique, the component side of the board is dedicated to
ground planes while signals are placed on the solder side.
In the example shown in Figure 32, the serial clock is taken from
the ESSI so the SCK0 pin must be set as an output (SCKD = 1).
The VDRIVE pin of the AD7904/AD7914/AD7924 takes the same
supply voltage as the DSP563xx. This allows the ADC to operate
at a higher voltage than the serial interface, that is, the DSP563xx,
if necessary.
DSP563xx*
AD7904/
AD7914/
AD7924*
SCLK
DOUT
CS
SCK
SRD
STD
SC2
Good decoupling is also important. All analog supplies should
be decoupled with 10 μF tantalum capacitors in parallel with
0.1 μF capacitors to AGND. To achieve the best performance
from these decoupling components, place them as close as
possible to the device, ideally right up against the device. The
0.1 μF capacitors should have low effective series resistance
(ESR) and effective series inductance (ESI), such as the common
ceramic types or surface-mount types, which provide a low
impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
DIN
V
DRIVE
V
DD
*ADDITIONAL PINS REMOVED FOR CLARITY.
Figure 32. Interfacing to the DSP563xx
Rev. C | Page 28 of 32
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