AD7891
TIMING CHARACTERISTICS
1, 2
Parameter
t
CONV
Parallel Interface
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9 3
t
104
Serial Interface
t
11
t
123
t
13
t
14
t
153
t
163
t
17
t
184
t
18A4
t
19
t
20
t
21
t
22
A, B, Y Versions
1.6
0
35
25
5
0
35
55
35
25
5
30
30
20
25
25
5
15
20
0
30
0
30
20
15
10
30
Units
µs
max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
Test Conditions/Comments
Conversion Time
CS
to
RD/WR
Setup Time
Write Pulsewidth
Data Valid to Write Setup Time
Data Valid to Write Hold Time
CS
to
RD/WR
Hold Time
CONVST
Pulsewidth
EOC
Pulsewidth
Read Pulsewidth
Data Access Time after Falling Edge of
RD
Bus Relinquish Time after Rising Edge of
RD
RFS
Low to SCLK Falling Edge Setup Time
RFS
Low to Data Valid Delay
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Rising Edge to Data Valid Hold Time
SCLK Rising Edge to Data Valid Delay
RFS
to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of
RFS
Bus Relinquish Time after Rising Edge of SCLK
TFS
Low to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Hold Time
TFS
Low to SCLK Falling Edge Hold Time
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to
90% of +5 V) and timed from a voltage level of +1.6 V.
2
See Figures 2, 3 and 4.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
TO
OUTPUT
PIN
+1.6V
50pF
200 A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
–4–
REV. A
AD [ ANALOG DEVICES ]
