AD7891
SERIAL INTERFACE MODE FUNCTIONS
When the part is configured for serial mode (MODE = 0), five of the 12 data input/output lines provide serial interface functions.
These functions are outlined below.
Mnemonic
SCLK
TFS
RFS
Description
Serial Clock Input. This is an externally applied serial clock which is used to load serial data to the control
register and to access data from the output register.
Transmit Frame Synchronization Pulse. Active low logic input with serial data expected after the falling
edge of this signal.
Receive Frame Synchronization Pulse. This is an active low logic input with
RFS
provided externally as a
strobe or framing pulse to access serial data from the output register. For applications that require that
data be transmitted and received at the same time,
RFS
and
TFS
should be connected together.
Serial Data Output. Sixteen bits of serial data are provided with the data FORMAT bit and the three
address bits of the control register preceding the 12 bits of conversion data. Serial data is valid on the
falling edge of SCLK for sixteen edges after
RFS
goes low. Output conversion data coding is twos comple-
ment when the FORMAT Bit of the control register is 1 and straight binary when the FORMAT Bit of the
control register is 0.
Serial Data Input. Serial data to be loaded to the control register is provided at this input. The first six bits
of serial data are loaded to the control register on the first six falling edges of SCLK after
TFS
goes low.
Serial data on subsequent SCLK edges is ignored while
TFS
remains low.
Test Pin. When the device is configured for serial mode of operation, two of the pins which had been data
inputs become test inputs. To ensure correct operation of the device, both TEST inputs should be tied to
a logic low potential.
DATA OUT
DATA IN
TEST
CONTROL REGISTER
The control register for the AD7891 contains 6 bits of information as described below. These 6 bits can be written to the control
register either in a parallel mode write operation or via a serial mode write operation. The default (power-on) condition of all bits in
the control register is 0. Six serial clock pulses must be provided to the part in order to write data to the control register. If
TFS
re-
turns high before six serial clock cycles then no data transfer takes place to the control register and the write cycle will have to be
restarted to write data to the control register. However, if the SWCONV bit of the register was previously set to a logic 1 and
TFS
is
brought high before six serial clock cycles, then another conversion will be initiated.
MSB
A2
A1
A0
SWCONV
SWSTBY
FORMAT
A2
A1
A0
Address Input. This input is the most significant address input for multiplexer channel selection.
Address Input. This is the second most significant address input for multiplexer channel selection.
Address Input. Least significant address input for multiplexer channel selection. When the address is written to
the control register, an internal pulse is initiated to allow for the multiplexer settling time and track/hold acquisi-
tion time before the track/hold goes into hold and conversion is initiated. When the internal pulse times out, the
track/hold goes into hold and conversion is initiated. The selected channel is given by the formula:
A2
×
4 +
A1
×
2 +
A0
+ 1
Conversion Start. Writing a 1 to this bit initiates a conversion in a similar manner to the
CONVST
input. Con-
tinuous conversion starts do not take place when there is a 1 in this location. The internal pulse and the conver-
sion process are initiated when a 1 is written to this bit. With a 1 in this bit, the hardware conversion start, i.e.,
the
CONVST
input, is disabled. Writing a 0 to this bit enables the hardware
CONVST
input.
Standby Mode Input. Writing a 1 to this bit places the device in its standby or power-down mode. Writing a 0 to
this bit places the device in its normal operating mode.
Data Format. Writing a 0 to this bit sets the conversion data output format to straight (natural) binary. This
data format is generally be used for unipolar input ranges. Writing a 1 to this bit sets the conversion data output
format to twos complement. This output data format is generally used for bipolar input ranges.
SWCONV
SWSTBY
FORMAT
REV. A
–9–
AD [ ANALOG DEVICES ]
