AD7858/AD7858L
Parameter
DYNAMIC PERFORMANCE
AV
DD,
DV
DD
I
DD
Normal Mode
5
Sleep Mode
6
With External Clock On
A Version
1
+3.0/+5.5
6 (1.9)
5.5 (1.9)
10
400
With External Clock Off
5
B Version
1
+3.0/+5.5
6 (1.9)
5.5 (1.9)
10
400
5
Units
V min/max
mA max
mA max
µA
typ
µA
typ
µA
max
µA
typ
mW max
mW max
µW
typ
µW
typ
µW
max
µW
max
V max/min
V max/min
AV
DD
= DV
DD
= 4.5 V to 5.5 V. Typically 4.5 mA (1.5)
AV
DD
= DV
DD
= 3.0 V to 3.6 V. Typically 4.0 mA (1.5 mA)
Full Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 0
Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1
Typically 1
µA.
Full Power-Down. Power Management Bits
in Control
Register Set as PMGT1 = 1, PMGT0 = 0
Partial Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 1
V
DD
= 5.5 V. Typically 25 mW (8);
SLEEP
= V
DD
V
DD
= 3.6 V. Typically 15 mW (5.4);
SLEEP
= V
DD
V
DD
= 5.5 V.
SLEEP
= 0 V
V
DD
= 3.6 V.
SLEEP
= 0 V
V
DD
= 5.5 V. Typically 5.5
µW;
SLEEP
= 0 V
V
DD
= 3.6 V. Typically 3.6
µW;
SLEEP
= 0 V
Allowable Offset Voltage Span for Calibration
Allowable Full-Scale Voltage Span for Calibration
Test Conditions/Comments
200
Normal-Mode Power Dissipation
Sleep Mode Power Dissipation
With External Clock On
With External Clock Off
SYSTEM CALIBRATION
Offset Calibration Span
7
Gain Calibration Span
7
33 (10.5)
20 (6.85)
55
36
27.5
18
200
33 (10.5)
20 (6.85)
55
36
27.5
18
+0.05
×
V
REF
/–0.05
×
V
REF
+1.025
×
V
REF
/–0.975
×
V
REF
NOTES
1
Temperature ranges as follows: A, B Versions: –40°C to +85°C. For L Versions, A and B Versions f
CLKIN
= 1 MHz over –40°C to +85°C temperature range,
B Version f
CLKIN
= 1.8 MHz over 0°C to +70°C temperature range.
2
Specifications apply after calibration.
3
SNR calculation includes distortion and noise components.
4
Sample tested @ +25°C to ensure compliance.
5
All digital inputs @ DGND except for
CONVST, SLEEP, CAL,
and
SYNC
@ DV
DD
. No load on the digital outputs. Analog inputs @ AGND.
6
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for
CONVST, SLEEP, CAL,
and
SYNC
@ DV
DD
. No load on the digital
outputs. Analog inputs @ AGND.
7
The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7858/AD7858L can calibrate. Note also that these are voltage
spans and are not absolute voltages ( i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
±
0.05
×
V
REF
, and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be
V
REF
±
0.025
×
V
REF
). This is explained in more detail in the Calibration section of the data sheet.
Specifications subject to change without notice.
REV. B
–3–
AD [ ANALOG DEVICES ]
