欢迎访问ic37.com |
会员登录 免费注册
发布采购

AD7811YRU 参数 Datasheet PDF下载

AD7811YRU图片预览
型号: AD7811YRU
PDF下载: 下载PDF文件 查看货源
内容描述: +2.7 V至+5.5 V , 350 kSPS时, 10位4- / 8通道采样ADC [+2.7 V to +5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCs]
分类和应用:
文件页数/大小: 19 页 / 211 K
品牌: ADI [ ADI ]
 浏览型号AD7811YRU的Datasheet PDF文件第11页浏览型号AD7811YRU的Datasheet PDF文件第12页浏览型号AD7811YRU的Datasheet PDF文件第13页浏览型号AD7811YRU的Datasheet PDF文件第14页浏览型号AD7811YRU的Datasheet PDF文件第16页浏览型号AD7811YRU的Datasheet PDF文件第17页浏览型号AD7811YRU的Datasheet PDF文件第18页浏览型号AD7811YRU的Datasheet PDF文件第19页  
AD7811/AD7812  
enter during automatic power-down. These modes are discussed  
in the Power-Up Times section of this data sheet. The timing  
diagram in Figure 17 shows how to operate the part in Mode 2.  
If the AD7811/AD7812 is powered down, the rising edge of the  
CONVST pulse causes the part to power-up. Once the part  
has powered up (~1.5 µs after the rising edge of CONVST)  
the CONVST signal is brought low and a conversion is initiated  
on this falling edge of the CONVST signal. The conversion  
takes 2.3 µs and after this time the conversion result is latched  
into the serial shift register and the part powers down. There-  
fore, when the part is operated in Mode 2 the effective conver-  
sion time is equal to the power-up time (1.5 µs) and the SAR  
conversion time (2.3 µs).  
(Point “B”), whichever occurs latest before initiating a serial  
read. The serial port of the AD7811 and AD7812 is still func-  
tional even though the devices have been powered down.  
Because it is possible to do a serial read from the part while it is  
powered down, the AD7811 and AD7812 are powered up only  
to do the conversion and are immediately powered down at the  
end of a conversion. This significantly improves the power  
consumption of the part at slower throughput rates—see Power  
vs. Throughput section.  
SERIAL INTERFACE  
The serial interface of the AD7811 and AD7812 consists of five  
wires, a serial clock input, SCLK, receive data to clock syn-  
chronization input RFS, transmit data to clock synchronization  
input TFS, a serial data output, DOUT, and a serial data  
input, DIN, (see Figure 18). The serial interface is designed to  
allow easy interfacing to most microcontrollers and DSPs,  
e.g., PIC16C, PIC17C, QSPI, SPI, DSP56000, TMS320  
and ADSP-21xx, without the need for any gluing logic. When  
interfacing to the 8051, the SCLK must be inverted. The  
Microprocessor/Microcontroller Interface section explains  
how to interface to some popular DSPs and microcontrollers.  
NOTE: Although the AD7811 and AD7812 take 1.5 µs to  
power up after the rising edge of CONVST, it is not necessary  
to leave CONVST high for 1.5 µs after the rising edge before  
bringing it low to initiate a conversion. If the CONVST signal  
goes low before 1.5 µs in time has elapsed, then the power-up  
time is timed out internally and a conversion is then initiated.  
Hence the AD7811 and AD7812 are guaranteed to have always  
powered-up before a conversion is initiated, even if the CONVST  
pulsewidth is <1.5 µs. If the CONVST pulsewidth is > 1.5 µs,  
then a conversion is initiated on the falling edge.  
Figure 18 shows the timing diagram for a serial read and write  
to the AD7811 and AD7812. The serial interface works with  
both a continuous and a noncontinuous serial clock. The rising  
edge of RFS and falling edge of TFS resets a counter that  
counts the number of serial clocks to ensure the correct number  
of bits are shifted in and out of the serial shift registers. Once  
the correct number of bits have been shifted in and out, the  
SCLK is ignored. In order for another serial transfer to take  
place the counter must be reset by the active edges of TFS and  
As in the case of Mode 1 operation, the rising edge of the first  
SCLK after the rising edge of RFS enables the serial port of the  
AD7811 and AD7812 (see Serial Interface section). If a serial  
read is initiated soon after this rising edge (Point “A”), i.e.,  
before the end of the conversion, the result of the previous con-  
version is shifted out on pin DOUT. In order to read the result  
of the current conversion, the user must wait at least 2.3 µs after  
power-up or at least 2.3 µs after the falling edge of CONVST,  
tPOWER-UP  
1.5s  
t1  
CONVST  
t2  
SCLK  
B
A
CURRENT CONVERSION  
RESULT  
DOUT  
Figure 17. Mode 2 Operation Timing Diagram  
t3  
2
A
B
SCLK  
4
5
6
7
8
9
10  
11  
12  
1
3
13  
t4  
t5  
RFS  
TFS  
t6  
t7  
t10  
DOUT  
DIN  
DB9  
DB9  
DB8  
DB7  
DB6  
DB5  
DB4  
DB3  
DB2  
DB1  
DB0  
t8  
t9  
DB8  
DB7  
DB6  
DB5  
DB4  
DB3  
DB2  
DB1  
DB0  
Figure 18. Serial Interface Timing Diagram  
–15–  
REV. B