AD7804/AD7805/AD7808/AD7809
(V
DD
= 3.3 V
= Internal Reference. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
6A
t
7
t
8
t
9
t
10
t
11
t
12
Limit at T
MIN
, T
MAX
All Versions
25
4.5
25
4.5
25
4.5
6
40
0
40
100
40
100
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
AD7805/AD7809 TIMING CHARACTERISTICS
1
10% to 5 V
10%; AGND = DGND = 0 V; Reference
Description
Mode Valid to Write Setup Time
Mode Valid to Write Hold Time
Address Valid to Write Setup Time
Address Valid to Write Hold Time
Data Setup Time
Data Hold Time
LDAC
Valid to Write Hold Time
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulsewidth
Time Between Successive Writes
LDAC, CLR
Pulsewidth
Write to
LDAC
Setup Time
NOTE
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (V
IL
+ V
IH
)/2.
Specifications subject to change without notice.
t
1
MODE
t
2
t
3
A0, A1, A2
t
4
CS
t
7
t
8
t
10
t
9
WR
t
5
DATA
t
6
t
6A
LDAC
1
t
12
LDAC
2
t
11
t
11
CLR
1
TIMING REQUIREMENTS FOR SYNCHRONOUS
LDAC
UPDATE OR
LDAC
MAY BE TIED PERMANENTLY LOW IF REQUIRED.
2
TIMING REQUIREMENTS FOR ASYNCHRONOUS
LDAC
UPDATE.
Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write
REV. A
–5–
AD [ ANALOG DEVICES ]
