AD7804/AD7805/AD7808/AD7809
AD7804/AD7808 TIMING CHARACTERISTICS
1
(V
Internal Reference. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
6A
t
7
t
8
t
9
Limit at T
MIN
, T
MAX
All Versions
100
40
40
30
30
5
6
90
20
40
100
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
Description
CLKIN Cycle Time
CLKIN High Time
CLKIN Low Time
FSIN
Setup Time
Data Setup Time
Data Hold Time
LDAC
Hold Time
FSIN
Hold Time
LDAC, CLR
Pulsewidth
LDAC
Setup Time
DD
=
3.3 V
10% to 5 V
10%; AGND = DGND = 0 V; Reference =
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (V
IL
+ V
IH
)/2.
Specifications subject to change without notice.
t
1
CLKIN(I)
t
2
t
4
FSIN(I)
t
3
t
7
t
5
t
6
SDIN(I)
DB15
DB0
t
5
LDAC
1
t
6A
LDAC
2
t
9
t
8
CLR
t
8
1
TIMING REQUIREMENTS FOR SYNCHRONOUS
LDAC
UPDATE OR
LDAC
MAY BE TIED PERMANENTLY LOW IF REQUIRED.
2
TIMING REQUIREMENTS FOR ASYNCHRONOUS
LDAC
UPDATE.
Figure 1. Timing Diagram for AD7804 and AD7808
–4–
REV. A
AD [ ANALOG DEVICES ]
