AD7715
TIMING CHARACTERISTICS
DV
DD
= 3 V to 5.25 V; AV
DD
= 3 V to 5.25 V; AGND = DGND = 0 V; f
CLKIN
= 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = DV
DD
, unless
otherwise noted.
Table 4.
Parameter
f
CLKIN 3, 4
t
CLK IN LO
t
CLK IN HI
t
1
t
2
Read Operation
t
3
t
4
t
5 5
Limit at T
MIN
, T
MAX
(A Version)
400
2.5
0.4 × t
CLK IN
0.4 × t
CLK IN
500 × t
CLK IN
100
0
120
0
80
100
100
100
0
10
60
100
100
120
30
20
100
100
0
Unit
kHz min
MHz max
ns min
ns min
ns nom
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
Master clock frequency: crystal oscillator or externally supplied for specified
performance
Master clock input low time; t
CLK IN
= 1/f
CLK IN
Master clock input high time
DRDY high time
RESET pulsewidth
DRDY to CS setup time
CS falling edge to SCLK rising edge setup time
SCLK falling edge to data valid delay
DV
DD
= 5 V
DV
DD
= 3.3 V
SCLK high pulsewidth
SCLK low pulsewidth
CS rising edge to SCLK rising edge hold time
Bus relinquish time after SCLK rising edge
DV
DD
= +5 V
DV
DD
= +3.3 V
SCLK falling edge to DRDY high
CS falling edge to SCLK rising edge setup time
Data valid to SCLK rising edge setup time
Data valid to SCLK rising edge hold time
SCLK high pulsewidth
SCLK low pulsewidth
CS rising edge to SCLK rising edge hold time
t
6
t
7
t
8
t
9 6
t
10
Write Operation
t
11
t
12
t
13
t
14
t
15
t
16
1
2
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
See Figure 8 and Figure 9.
3
CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7715 is not in standby mode. If no clock is present in this case, the device can draw
higher current than specified and possibly become uncalibrated.
4
The AD7715 is production tested with f
CLKIN
at 2.4576 MHz (1 MHz for some I
DD
tests). It is guaranteed by characterization to operate at 400 kHz.
5
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
7
DRDY
returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although take care that
subsequent reads do not occur close to the next output update.
I
SINK
(800µA AT DV
DD
= 5V
100µA AT DV
DD
= 3.3V)
TO
OUTPUT
PIN
+1.6V
50pF
I
SOURCE
(200µA AT DV
DD
= 5V
100µA AT DV
DD
= 3.3V)
08519-002
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
Rev. D | Page 8 of 40
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