AD7715
AV
DD
= 3 V to 5 V, DV
DD
= 3 V to 5 V, REF IN(+) = 1.25 V (AD7715-3) or 2.5 V (AD7715-5); REF IN(−) = AGND; MCLK IN = 1 MHz to
2.4576 MHz, unless otherwise noted. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
Negative Full-Scale Calibration Limit
Offset Calibration Limit
Input Span
2
0.8 ×
V
REF
/GAIN
(2.1 × V
REF
)/GAIN
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage (AD7715-3)
AV
DD
Voltage (AD7715-5)
DV
DD
Voltage
Power Supply Currents
AV
DD
Current
Min
Typ
Max
(1.05 ×
V
REF
)/GAIN
−(1.05 ×
V
REF
)/GAIN
−(1.05 ×
V
REF
)/GAIN
Unit
V
V
V
V
V
Conditions/Comments
GAIN Is the selected PGA gain (1, 2, 32, or 128)
GAIN Is the selected PGA gain (1, 2, 32, or 128)
GAIN Is the selected PGA gain (1, 2, 32, or 128)
GAIN Is the selected PGA gain (1, 2, 32, or 128)
GAIN Is the selected PGA gain (1, 2, 32, or 128)
3
4.75
3
3.6
5.25
5.25
V
V
V
For specified performance
For specified performance
For specified performance
AV
DD
= 3.3 V or 5 V. gain = 1 to 128 (f
CLK IN
= 1 MHz) or
gain = 1 or 2 (f
CLK IN
= 2.4576 MHz)
Typically 0.2 mA; BUF bit of the setup register = 0
Typically 0.4 mA; BUF bit of the setup register = 1, AV
DD
= 3.3 V or 5 V; gain = 32 or 128 (f
CLK IN
= 2.4576 MHz)
Typically 0.3 mA; BUF bit of the setup register = 0
Typically 0.8 mA; BUF bit of the setup register = 1
Digital inputs = 0 V or DV
DD
; external MCLK IN
Typically 0.15 mA. DV
DD
= 3.3 V. f
CLK IN
= 1 MHz
Typically 0.3 mA. DV
DD
= 5 V. f
CLK IN
= 1 MHz
Typically 0.4 mA. DV
DD
= 3.3 V. f
CLK IN
= 2.4576 MHz
Typically 0.6 mA. DV
DD
= 5 V. f
CLK IN
= 2.4576 MHz
AV
DD
= DV
DD
= 3.3 V; digital inputs = 0 V or DV
DD
; external
MCLK IN
BUF bit = 0. all gains 1 MHz clock
BUF bit = 1. all gains 1 MHz clock
BUF bit = 0. Gain = 32 or 128 @ f
CLK IN
= 2.4576 MHz
BUF bit = 1. Gain = 32 or 128 @ f
CLK IN
= 2.4576 MHz
AV
DD
= DV
DD
= 5 V. digital inputs = 0 V or DV
DD
; external
MCLK IN
BUF bit = 0; all gains 1 MHz clock
BUF bit = 1; all gains 1 MHz clock
BUF bit = 0; gain = 32 or 128 @ f
CLK IN
= 2.4576 MHz
BUF bit = 1; gain = 32 or 128 @ f
CLK IN
= 2.4576 MHz
External MCLK IN = 0 V or DV
DD
. typically 10 μA; V
DD
= 5 V
External MCLK IN = 0 V or DV
DD
. typically 5 μA; V
DD
= 3.3 V
0.27
0.6
0.5
1.1
DV
DD
Current
0.18
0.4
0.5
0.8
Depends on gain
mA
mA
mA
mA
mA
mA
mA
mA
dB
Power Supply Rejection
Normal-Mode Power Dissipation
1.5
2.65
3.3
5.3
Normal-Mode Power Dissipation
3.25
5
6.5
9.5
20
10
mW
mW
mW
mW
Standby (Power-Down) Current
Standby (Power-Down) Current
7
1
mW
mW
mW
mW
μA
μA
After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, then the device outputs
all 0s.
2
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30 mV or go more negative than AGND − 30 mV.
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
3
Assumes CLK Bit of setup register is set to correct status corresponding to the master clock frequency.
4
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV
DD
current and power dissipation will vary depending on the
crystal or resonator type (see the Clocking and Oscillator Circuit section).
5
Measured at dc and applies in the selected pass-band. PSRR at 50 Hz exceeds 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB with filter
notches of 20 Hz or 60 Hz.
6
PSRR depends on gain. Gain of 1:85 dB typical; gain of 2:90 dB typical; gains of 32 and 128:95 dB typical.
7
If the external master clock continues to run in standby mode, the standby current increases to 50 μA typical. When using a crystal or ceramic resonator across the
MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator
type (see the Standby Mode section).
Rev. D | Page 7 of 40
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