AD7714
(AVDD = DVDD = +2.7 V to +5.25 V; AGND = DGND = 0 V; fCLKIN = 2.5 MHz; Input Logic 0 = 0 V,
Logic 1 = DVDD unless otherwise noted.)
TIMING CHARACTERISTICS1, 2
Limit at TMIN, TMAX
Parameter
(A, Y Versions)
Units
Conditions/Comments
3, 4
fCLKIN
400
kHz min
Master Clock Frequency: Crystal/Resonator or Externally
Supplied
2.5
MHz max
ns min
ns min
ns nom
ns min
ns min
For Specified Performance
Master Clock Input Low Time. tCLK IN = 1/fCLK IN
Master Clock Input High Time
DRDY High Time
SYNC Pulsewidth
RESET Pulsewidth
2
tCLK IN LO
tCLK IN HI
tDRDY
t1
0.4 × tCLK IN
0.4 × tCLK IN
500 × tCLK IN
100
t2
100
Read Operation
t3
0
0
0
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns max
DRDY to CS Setup Time
t46
CS Falling Edge to SCLK Active Edge Setup Time5
SCLK Active Edge to Data Valid Delay5
DVDD = +5 V
t5
80
100
100
100
0
10
60
100
100
DVDD = +3 V
SCLK High Pulsewidth
t6
t7
SCLK Low Pulsewidth
t87
CS Rising Edge to SCLK Active Edge Hold Time5
Bus Relinquish Time after SCLK Active Edge5
DVDD = +5 V
t9
DVDD = +3 V
t10
SCLK Active Edge to DRDY High5, 8
Write Operation
t11
t12
t13
t14
t15
t16
0
ns min
ns min
ns min
ns min
ns min
ns min
CS Falling Edge to SCLK Active Edge Setup Time5
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to SCLK Edge Hold Time
30
20
100
100
0
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV DD) and timed from a voltage level of 1.6 V.
2See Figures 6 and 7. Timing applies for all grades.
3CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7714 is not in standby mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
4The AD7714 is production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). It is guaranteed by characterization to operate at 400 kHz.
5SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.
6These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V OL or VOH limits.
7These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
8DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although care
should be taken that subsequent reads do not occur close to the next output update.
Specifications subject to change without notice.
ORDERING GUIDE
AVDD
Supply Range
Temperature
Package
Option*
Model
AD7714AN-5
AD7714AR-5
AD7714ARS-5
AD7714AN-3
AD7714AR-3
AD7714ARS-3
AD7714YN
5 V
5 V
5 V
3 V
3 V
3 V
–40°C to +85°C
N-24
R-24
RS-28
N-24
R-24
RS-28
N-24
R-24
RU-24
Die
I
(800A AT DV = +5V
DD
SINK
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
100A AT DV = +3.3V)
DD
TO OUTPUT
PIN
+1.6V
50pF
3 V/5 V –40°C to +105°C
3 V/5 V –40°C to +105°C
3 V/5 V –40°C to +105°C
5 V
3 V
AD7714YR
I
(200A AT DV = +5V
DD
SOURCE
AD7714YRU
AD7714AChips-5
AD7714AChips-3
EVAL-AD7714-5EB 5 V
EVAL-AD7714-3EB 3 V
100A AT DV = +3.3V)
DD
–40°C to +85°C
–40°C to +85°C
Evaluation Board
Evaluation Board
Die
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
*N = Plastic DIP; R = SOIC; RS = SSOP; RU = Thin Shrink Small Outline.
REV. C
–7–
ADI [ ADI ]
