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AD7714ARS-5 参数 Datasheet PDF下载

AD7714ARS-5图片预览
型号: AD7714ARS-5
PDF下载: 下载PDF文件 查看货源
内容描述: 3 V / 5 V , CMOS , 500微安信号调理ADC [3 V/5 V, CMOS, 500 uA Signal Conditioning ADC]
分类和应用: 转换器光电二极管
文件页数/大小: 40 页 / 308 K
品牌: ADI [ ADI ]
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AD7714  
PIN FUNCTION DESCRIPTION (Continued)  
Pin  
No. Mnemonic  
Function  
19 CS  
Chip Select. Active low Logic Input used to select the AD7714. With this input hard-wired low, the AD7714  
can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the device. CS  
can be used to select the device in systems with more than one device on the serial bus or as a frame  
synchronization signal in communicating with the AD7714.  
20 DRDY  
Logic output. A logic low on this output indicates that a new output word is available from the AD7714 data  
register. The DRDY pin will return high upon completion of a read operation of a full output word. If no data  
read has taken place, after an output update, the DRDY line will return high for 500 × tCLK IN cycles prior to  
the next output update. This gives an indication of when a read operation should not be attempted to avoid  
reading from the data register as it is being updated. DRDY is also used to indicate when the AD7714 has  
completed its on-chip calibration sequence.  
21 DOUT  
22 DIN  
Serial Data Output with serial data being read from the output shift register on the part. This output shift  
register can contain information from the calibration registers, mode register, communications register, filter  
selection registers or data register depending on the register selection bits of the Communications Register.  
Serial Data Input with serial data being written to the input shift register on the part. Data from this input shift  
register is transferred to the calibration registers, mode register, communications register or filter selection  
registers depending on the register selection bits of the Communications Register.  
23 DVDD  
Digital Supply Voltage, A Grade Versions: +3.3 V or +5 V nominal; Y Grade Versions: 3 V or 5 V nominal.  
24 DGND  
Ground reference point for digital circuitry.  
BIPOLAR NEGATIVE FULL-SCALE ERROR  
TERMINOLOGY*  
This is the deviation of the first code transition from the ideal  
AIN(+) voltage (AIN(–) – VREF/GAIN + 0.5 LSB) when operat-  
ing in the bipolar mode.  
INTEGRAL NONLINEARITY  
This is the maximum deviation of any code from a straight line  
passing through the endpoints of the transfer function. The end-  
points of the transfer function are zero scale (not to be confused  
with bipolar zero), a point 0.5 LSB below the first code transi-  
tion (000 . . . 000 to 000 . . . 001) and full scale, a point  
0.5 LSB above the last code transition (111 . . . 110 to  
111 . . . 111). The error is expressed as a percentage of full  
scale.  
POSITIVE FULL-SCALE OVERRANGE  
Positive Full-Scale Overrange is the amount of overhead avail-  
able to handle input voltages on AIN(+) input greater than  
AIN(–) + VREF/GAIN (for example, noise peaks or excess volt-  
ages due to system gain errors in system calibration routines)  
without introducing errors due to overloading the analog modu-  
lator or overflowing the digital filter.  
POSITIVE FULL-SCALE ERROR  
Positive Full-Scale Error is the deviation of the last code transi-  
tion (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage  
(AIN(–) + VREF/GAIN – 3/2 LSBs). It applies to both unipolar  
and bipolar analog input ranges.  
NEGATIVE FULL-SCALE OVERRANGE  
This is the amount of overhead available to handle voltages on  
AIN(+) below AIN(–) – VREF/GAIN without overloading the  
analog modulator or overflowing the digital filter. Note that the  
analog input will accept negative voltage peaks even in the uni-  
polar mode provided that AIN(+) is greater than AIN(–) and  
greater than AGND – 30 mV.  
UNIPOLAR OFFSET ERROR  
Unipolar Offset Error is the deviation of the first code transition  
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-  
ating in the unipolar mode.  
OFFSET CALIBRATION RANGE  
In the system calibration modes, the AD7714 calibrates its  
offset with respect to the analog input. The Offset Calibration  
Range specification defines the range of voltages that the  
AD7714 can accept and still calibrate offset accurately.  
BIPOLAR ZERO ERROR  
This is the deviation of the midscale transition (0111 . . . 111  
to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) –  
0.5 LSB) when operating in the bipolar mode.  
FULL-SCALE CALIBRATION RANGE  
This is the range of voltages that the AD7714 can accept in the  
system calibration mode and still calibrate full scale correctly.  
GAIN ERROR  
This is a measure of the span error of the ADC. It includes full-  
scale errors but not zero-scale errors. For unipolar input ranges  
it is defined as (full-scale error – unipolar offset error) while for  
bipolar input ranges it is defined as (full-scale error – bipolar  
zero error).  
INPUT SPAN  
In system calibration schemes, two voltages applied in sequence  
to the AD7714’s analog input define the analog input range.  
The input span specification defines the minimum and maxi-  
mum input voltages from zero to full scale that the AD7714 can  
accept and still calibrate gain accurately.  
*AIN(–) refers to the negative input of the differential input pairs or to AIN6  
when referring to the pseudo-differential input configurations.  
–10–  
REV. C  
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