AD7714
(AVDD = +3.3 V, DVDD = +3.3 V, REF IN(+) = +1.25 V; REF IN(–) = AGND;
fCLK IN = 2.4576 MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
AD7714-3–SPECIFICATIONS
Parameter
A Versions
Units
Conditions/Comments
STATIC PERFORMANCE
No Missing Codes
24
22
18
15
Bits min
Bits min
Bits min
Bits min
Bits min
Guaranteed by Design. Bipolar Mode. For Filter Notches ≤ 60 Hz
For Filter Notch = 100 Hz
For Filter Notch = 250 Hz
For Filter Notch = 500 Hz
For Filter Notch = 1 kHz
12
Output Noise
See Tables I to IV
Depends on Filter Cutoffs and Selected Gain
Filter Notches ≤ 60 Hz
Integral Nonlinearity
Unipolar Offset Error
Unipolar Offset Drift3
±0.0015
See Note 2
0.4
% of FSR max
µV/°C typ
µV/°C typ
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
0.1
Bipolar Zero Error
Bipolar Zero Drift3
See Note 2
0.4
0.1
See Note 2
0.4
0.1
See Note 2
0.2
±0.003
1
µV/°C typ
µV/°C typ
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Positive Full-Scale Error4
Full-Scale Drift3, 5
µV/°C typ
µV/°C typ
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Gain Error6
Gain Drift3, 7
ppm of FSR/°C typ
% of FSR max
µV/°C typ
Bipolar Negative Full-Scale Error
Typically ±0.0004%
For Gains of 1, 2, 4
Bipolar Negative Full-Scale Drift3
0.6
µV/°C typ
For Gains of 8, 16, 32, 64, 128
ANALOG INPUTS/REFERENCE INPUTS
Input Common-Mode Rejection (CMR)
Normal-Mode 50 Hz Rejection8
Normal-Mode 60 Hz Rejection8
Common-Mode 50 Hz Rejection8
Common-Mode 60 Hz Rejection8
Common-Mode Voltage Range9
Absolute AIN/REF IN Voltage9
Specifications for AIN and REF IN Unless Noted
At DC. Typically 102 dB.
90
100
100
150
dB min
dB min
dB min
dB min
dB min
V min to V max
V min
V max
V min
V max
nA max
pF max
For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 × fNOTCH
For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 × fNOTCH
For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 × fNOTCH
For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 × fNOTCH
AIN for BUFFER = 0 and REF IN
150
AGND to AVDD
AGND – 30 mV
AVDD + 30 mV
AGND + 50 mV
AVDD – 1.5 V
1
AIN for BUFFER = 0 and REF IN
Absolute/Common-Mode AIN Voltage9
BUFFER = 1
AIN Input Current8
AIN Sampling Capacitance8
AIN Differential Voltage Range10
7
0 to +VREF/GAIN11 nom
Unipolar Input Range (B/U Bit of Filter High Register = 1)
Bipolar Input Range (B/U Bit of Filter High Register = 0)
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
±1% for Specified Performance. Part Functions with
Lower VREF
±VREF/GAIN
GAIN × fCLK IN/64
fCLK IN/8
nom
AIN Input Sampling Rate, fS
REF IN(+) – REF IN(–) Voltage
REF IN Input Sampling Rate, fS
+1.25
V nom
fCLK IN/64
LOGIC INPUTS
Input Current
±10
µA max
All Inputs Except MCLK IN
VINL, Input Low Voltage
VINH, Input High Voltage
MCLK IN Only
VINL, Input Low Voltage
VINH, Input High Voltage
0.4
2.0
V max
V min
0.4
2.5
V max
V min
LOGIC OUTPUTS (Including MCLK OUT)
VOL, Output Low Voltage
VOH, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance13
Data Output Coding
0.4
DVDD – 0.6
±10
V max
V min
µA max
pF typ
ISINK = 100 µA Except for MCLK OUT12
ISOURCE = 100 µA Except for MCLK OUT12
9
Binary
Offset Binary
Unipolar Mode
Bipolar Mode
NOTES
7Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with
background calibration.
8These numbers are guaranteed by design and/or characterization.
9The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.
10The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII
for which inputs form differential pairs.
11
V
REF
= REF IN(+) – REF IN(–).
12These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.
13Sample tested at +25°C to ensure compliance.
14See Burnout Current section.
–3–
REV. C
ADI [ ADI ]
