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AD7714ARS-5 参数 Datasheet PDF下载

AD7714ARS-5图片预览
型号: AD7714ARS-5
PDF下载: 下载PDF文件 查看货源
内容描述: 3 V / 5 V , CMOS , 500微安信号调理ADC [3 V/5 V, CMOS, 500 uA Signal Conditioning ADC]
分类和应用: 转换器光电二极管
文件页数/大小: 40 页 / 308 K
品牌: AD [ ANALOG DEVICES ]
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AD7714
AD7714-3–SPECIFICATIONS
(AV
f
= 2.4576 MHz unless otherwise noted. All specifications T
CLK IN
= +3.3 V, DV
DD
= +3.3 V, REF IN(+) = +1.25 V; REF IN(–) = AGND;
MIN
to T
MAX
unless otherwise noted.)
DD
Parameter
STATIC PERFORMANCE
No Missing Codes
A Versions
24
22
18
15
12
See Tables I to IV
±
0.0015
See Note 2
0.4
0.1
See Note 2
0.4
0.1
See Note 2
0.4
0.1
See Note 2
0.2
±
0.003
1
0.6
90
100
100
150
150
AGND to AV
DD
AGND – 30 mV
AV
DD
+ 30 mV
AGND + 50 mV
AV
DD
– 1.5 V
1
7
0 to +V
REF
/GAIN
11
±
V
REF
/GAIN
GAIN
×
f
CLK IN
/64
f
CLK IN
/8
+1.25
f
CLK IN
/64
±
10
0.4
2.0
0.4
2.5
0.4
DV
DD
– 0.6
±
10
9
Binary
Offset Binary
Units
Bits min
Bits min
Bits min
Bits min
Bits min
% of FSR max
µV/°C
typ
µV/°C
typ
µV/°C
typ
µV/°C
typ
µV/°C
typ
µV/°C
typ
ppm of FSR/°C typ
% of FSR max
µV/°C
typ
µV/°C
typ
dB min
dB min
dB min
dB min
dB min
V min to V max
V min
V max
V min
V max
nA max
pF max
nom
nom
Conditions/Comments
Guaranteed by Design. Bipolar Mode. For Filter Notches
60 Hz
For Filter Notch = 100 Hz
For Filter Notch = 250 Hz
For Filter Notch = 500 Hz
For Filter Notch = 1 kHz
Depends on Filter Cutoffs and Selected Gain
Filter Notches
60 Hz
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Typically
±
0.0004%
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Specifications for AIN and REF IN Unless Noted
At DC. Typically 102 dB.
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
AIN for BUFFER = 0 and REF IN
AIN for BUFFER = 0 and REF IN
BUFFER = 1
Output Noise
Integral Nonlinearity
Unipolar Offset Error
Unipolar Offset Drift
3
Bipolar Zero Error
Bipolar Zero Drift
3
Positive Full-Scale Error
4
Full-Scale Drift
3, 5
Gain Error
6
Gain Drift
3, 7
Bipolar Negative Full-Scale Error
Bipolar Negative Full-Scale Drift
3
ANALOG INPUTS/REFERENCE INPUTS
Input Common-Mode Rejection (CMR)
Normal-Mode 50 Hz Rejection
8
Normal-Mode 60 Hz Rejection
8
Common-Mode 50 Hz Rejection
8
Common-Mode 60 Hz Rejection
8
Common-Mode Voltage Range
9
Absolute AIN/REF IN Voltage
9
Absolute/Common-Mode AIN Voltage
9
AIN Input Current
8
AIN Sampling Capacitance
8
AIN Differential Voltage Range
10
AIN Input Sampling Rate, f
S
REF IN(+) – REF IN(–) Voltage
REF IN Input Sampling Rate, f
S
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
13
Data Output Coding
f
NOTCH
f
NOTCH
f
NOTCH
f
NOTCH
V nom
Unipolar Input Range (B/U Bit of Filter High Register = 1)
Bipolar Input Range (B/U Bit of Filter High Register = 0)
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
±
1% for Specified Performance. Part Functions with
Lower V
REF
µA
max
V max
V min
V max
V min
V max
V min
µA
max
pF typ
I
SINK
= 100
µA
Except for MCLK OUT
12
I
SOURCE
= 100
µA
Except for MCLK OUT
12
Unipolar Mode
Bipolar Mode
NOTES
7
Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with
background calibration.
8
These numbers are guaranteed by design and/or characterization.
9
The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.
10
The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII
for which inputs form differential pairs.
11
V
REF
= REF IN(+) – REF IN(–).
12
These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.
13
Sample tested at +25°C to ensure compliance.
14
See Burnout Current section.
REV. C
–3–