AD7606/AD7606-6/AD7606-4
Parameter
t
27
Limit at T
MIN
, T
MAX
Min
Typ
Max
19
24
t
28
17
22
24
ns
ns
ns
Unit
ns
ns
Description
Delay from RD falling edge to FRSTDATA low
V
DRIVE
= 3.3 V to 5.25V
V
DRIVE
= 2.3 V to 2.7V
Delay from 16
th
SCLK falling edge to FRSTDATA low
V
DRIVE
= 3.3 V to 5.25V
V
DRIVE
= 2.3 V to 2.7V
Delay from CS rising edge until FRSTDATA three-state enabled
t
29
1
2
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DRIVE
) and timed from a voltage level of 1.6 V.
In oversampling mode, typical t
CONV
for the AD7606-6 and AD7606-4 can be calculated using ((N × t
CONV
) + ((N − 1) × 1 μs)). N is the oversampling ratio. For the AD7606-6,
t
CONV
= 3 μs; and for the AD7606-4, t
CONV
= 2 μs.
3
The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets.
4
A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
Timing Diagrams
t
5
CONVST A,
CONVST B
CONVST A,
CONVST B
t
CYCLE
t
3
t
1
t
CONV
t
2
BUSY
t
4
CS
RESET
t
7
08479-002
t
RESET
Figure 2. CONVST Timing—Reading After a Conversion
t
5
CONVST A,
CONVST B
t
CYCLE
CONVST A,
CONVST B
t
2
t
3
t
CONV
t
1
BUSY
t
6
CS
t
7
08479-003
t
RESET
RESET
Figure 3. CONVST Timing—Reading During a Conversion
CS
t
8
RD
t
10
t
11
t
9
t
16
t
14
t
15
V4
V7
V8
t
13
t
17
DATA:
DB[15:0]
INVALID
V1
V2
V3
FRSTDATA
t
24
Figure 4. Parallel Mode, Separate CS and RD Pulses
Rev. 0 | Page 9 of 36
08479-004
t
26
t
27
t
29
AD [ ANALOG DEVICES ]
