AD7528
V
IN
A
(± 10V)
R1
1
R2
1
V
DD
DB0
DATA
INPUTS
DB7
INPUT
BUFFER
LATCH
DAC A
R
FB
A
OUT A
AGND
AGND
C1
2
V
OUT
A
Table I. Unipolar Binary Code Table
DAC Latch Contents
MSB
LSB
11111111
10000001
10000000
V
OUT
B
AGND
Analog Output
(DAC A or DAC B)
255
–V
IN
256
129
–V
IN
256
V
128
–V
IN
= −
IN
256
2
127
–V
IN
256
1
–V
IN
256
0
–V
IN
=
0
256
1
(
V
)
256
IN
DAC A/
DAC B
CS
WR
DGND
AD7528
CONTROL
LOGIC
LATCH
DAC B
R4
1
R
FB
B
OUT B
C2
2
01111111
00000001
00000000
Note: 1 LSB =
2
−8
(
V
IN
)
=
R3
1
V
IN
B
(± 10V)
NOTES:
1
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE III FOR RECOMMENDED VALUES.
2
C1, C2 PHASE COMPENSATION (10pF–15pF) IS REQUIRED WHEN
USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.
( )
Figure 4. Dual DAC Unipolar Binary Operation
(2 Quadrant Multiplication); See Table I
V
IN
A
(± 10V)
R5
20k
R1
1
R2
1
V
DD
DB0
DATA
INPUTS
DB7
INPUT
BUFFER
LATCH
DAC A
R
FB
A
OUT A
AGND
AGND
DAC A/
DAC B
CS
WR
DGND
R6
2
20k
R7
2
10k
C1
3
A1
A2
R11
5k
AGND
V
OUT
A
Table II. Bipolar (Offset Binary) Code Table
DAC Latch Contents Analog Output
MSB
LSB
(DAC A or DAC B)
11111111
10000001
10000000
0
1
–V
IN
128
127
–V
IN
128
128
–V
IN
128
1
(
V
)
128
IN
127
+V
IN
128
AD7528
CONTROL
LOGIC
LATCH
DAC B
R4
1
R
FB
B
OUT B
AGND
R3
1
C2
3
A3
R9
2
10k
R10
2
20k
A4
R12
5k
AGND
V
OUT
B
R8
20k
01111111
00000001
00000000
Note: 1 LSB =
2
−7
(
V
IN
)
=
V
IN
B
(± 10V)
NOTES:
1
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE III FOR RECOMMENDED VALUES.
ADJUST R1 FOR V
OUT
A = 0V WITH CODE 10000000 IN DAC A LATCH.
ADJUST R3 FOR V
OUT
B = 0V WITH CODE 10000000 IN DAC B LATCH.
2
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R6, R7 AND R9, R10.
3
C1, C2 PHASE COMPENSATION (10pF–15pF) MAY BE REQUIRED
IF A1/A3 IS A HIGH SPEED AMPLIFIER.
( )
Table III. Recommended Trim Resistor
Values vs. Grade
Figure 5. Dual DAC Bipolar Operation
(4 Quadrant Multiplication); See Table II
Trim
Resistor
R1; R3
R2; R4
J/A/S
1k
330
K/B/T
500
150
L/C/U
200
82
REV. B
–5–
AD [ ANALOG DEVICES ]
