AD6620
tDPR
real mode with full rate timing the delay is seven CLKs. If
instead the data rate is one-fourth CLK, then 28 CLKs (i.e.,
seven sample data delays, gated via A/B) occur before valid data
is passed to the NCO stage.
tDPF
tDPF
CLK
Interfacing AD6620 Inputs to 5 V Logic Gates
DV
OUT
VALID DATA
None of the inputs to the AD6620 are tolerant of 5 V logic
signals. When interfacing 5 V devices to this product, an interface
gate such as the 74LCX2244 is recommended. If latching must
be performed, 74LCX574 latches may be used. This gate runs
from the 3.3 V supply and is tolerant of 5 V inputs.
I/Q
I
Q
OUT
A/B
OUT
A DATA
Q
OUTPUT DATA PORT
Parallel Output Data Port
OUT[15:0]
I
A
A
The AD6620 provides a choice of two output ports: a 16-bit
parallel port and a synchronous serial port. Output operation
using the serial port is discussed in the next section. The parallel
port is limited to 16 bits. Because pins are shared between the
parallel and serial output ports, only one output mode can be
used. The output mode must be set with a hard reset generated
by at least a 30 ns low time on the RESET pin. If the PAR/SER
line is high (Logic “1”), then parallel output data is activated.
The PAR/SER pin should remain static after the output mode
has been set (i.e., PAR/SER should only change when RESET is
low). Data out of the AD6620 is two’s complement.
Figure 28. Parallel Output Data Timing (Single-Channel
Mode)
tDPR
tDPF
tDPF
tDPF
CLK
DV
OUT
VALID DATA
A scale factor is associated with the output port, which allows
the signal level to be adjusted. This scale factor is mapped to
location 309h, Bits 2–0 in the AD6620 internal address space.
This scalar controls the weight of the 16-bit data going to the
parallel port. The scale factor is discussed in the RAM Coeffi-
cient Filter (RCF) section.
I/Q
I
Q
I
Q
OUT
A/B
A DATA
B DATA
OUT
I
Q
I
Q
B
OUT[15:0]
A
A
B
The Parallel Mode provides a 16-bit output port, which consti-
tutes the I and Q data for either one or both channels. This port
can run at a maximum of 67 MHz (33.5 MHz I, 33.5 MHz Q).
Figure 29. Parallel Output Data Timing (Diversity Channel
Mode)
This rate assumes that there is a minimum decimation of 2 in
the first filter stage (CIC2) or a 2× or greater CLK is used. This
decimation is required because for every input word there is
both an I and a Q output. When the data rate and clock rate are
the same (Full Rate Input Timing), the minimum decimation of
2 must occur in CIC2. Refer to CIC2 for more detail.
Serial Output Data Port
The AD6620 provides a choice of two output ports: a 16-bit
parallel port and a synchronous serial port. The advantage of
using the serial port is that all 23 bits of available data can be
output in the 24-bit or 32-bit mode. The serial output port
shares some of the same pins used by the parallel output port.
As a result, one or the other mode of output may be utilized,
but not both. The output mode must be set with a hard reset
generated by at least a 30 ns low time on the RESET pin. If the
PAR/SER line is low (Logic “0”) upon reset, then serial output
data is activated. The PAR/SER pin should remain static after
the output mode has been set (i.e., PAR/SER should only change
when RESET is low).
DVOUT
DVOUT is provided to signal that valid data is present. If this pin
is high, there is a valid data word on the bus. DVOUT remains high
for two high-speed clock cycles in Single Channel Real and Single
Channel Complex Mode and for four high-speed clock cycles in
Diversity Channel Real mode. After DVOUT returns low the Q data
will remain until the next data sample.
Note that the AD6620 cannot be booted through the serial port.
The microport must be used to initialize the device, then serial
operation is supported.
I/QOUT
When this pin is high the data word represents I data; when
I/QOUT is low Q data is present. This signal will also be low when
DVOUT is low since the last word of every data phase is Q data.
Figure 30 shows the typical interconnections between an AD6620
in serial master mode and a DSP. Refer to the Serial Control
Port section for a detailed description of pin functions and pro-
cedures for writing and reading with relation to the serial port.
Note the 10 kΩ resistors connected to SDI and SDO. These
prevent the lines from toggling when the AD6620 or DSP
three-states these pins.
A/BOUT
If DVOUT is low, A/BOUT is always low. When A/BOUT is high, A
Channel data is available on the output. If DVOUT remains high
while A/BOUT is low, then B Channel data is on the output pins
of the chip OUT[15:0].
REV. A
–18–
ADI [ ADI ]
