AD6620
Single Channel Complex Mode
CLK
In the Single Channel Complex input mode, A/B high identi-
fies the in-phase samples and A/B low identifies quadrature
samples. The quadrature samples are paired with the previous
in-phase samples. The timing for this mode is the same as that
of the Diversity Channel Real Mode. This mode is useful for
accepting complex output data from another AD6620 or another
source to increase filtering and or decimation rates.
tHI
tSI
IN[15:0]
A
B
A
B
A
B
N+2
N
N
N+1
N+1
N+2
EXP[2:0]
A/B
In the Single Channel Complex Mode the CIC2 decimation
must be set to two (MCIC2 = 2). This is necessary in order to
allow enough CLK cycles to process the complex input data as
described below.
CLK
2x
IF CLK 2x IS USED TO CLOCK THE AD6620, THE FIRST RISING EDGE AFTER
THE A/B TRANSITION WILL LATCH THE DATA.
First clock cycle: (A/B high).
– I data loaded from the input port.
– The I data-path gets I × cosine.
– The Q data-path gets I × sine.
– The first integrator of the CIC2 adds these values to its
previous sums.
Figure 25. Full Rate Input Timing, Diversity Channel Real
Mode
If fractional rate input timing is necessary in the Diversity Chan-
nel Real Mode, the A/B pin must toggle at half the rate of the
A/D sample clock. The timing diagram below shows a 3× pro-
cessing clock. In this situation there will be one ADC encode
pulse for every three AD6620 CLK pulses and data must be
taken on every third CLK pulse. The CLK edges that corre-
spond to the latching of A and B channel data are shown in
Figure 26.
– The rest of the CIC2 is idle.
Second clock cycle: (A/B low).
– Q data loaded from the input port.
– The I data-path gets Q × sine.
– The Q data-path gets Q × cosine.
– The first integrator of the I path of the CIC2 completes the
sum (I × cosine - Q × sine) and the first integrator of the Q
path of the CIC2 completes the sum j(I × sine + Q × cosine).
– The rest of the CIC2 operates on these sums, which is the
complete complex multiply. The data is then multiplexed
through the rest of the chip as if it were single channel real data.
CLK
tHI
tSI
IN[15:0]
A
B
N
N
EXP[2:0]
Simplified Input Data Port Schematic
Figure 27 details a simplified schematic for the input data port.
The first thing to note is that IN[15:0], EXP[2:0] and A/B are
all synchronously latched with CLK. Note also that upon soft
reset, a seven pipeline delay (sample clock delay) exists in the
data path. This delay is synchronous with CLK, but is in fact
seven valid sample data delays. For instance, in single channel
A/B
Figure 26. Fractional Rate Input Timing (3× CLK), Diversity
Channel Real Mode
SOFT RESET
CLR
LOGIC "1"
D
Q
DELAY 7
ENB
CLK
Q
IN[15:0]
CLR
INT IN[15:0]
INT EXP[2:0]
D
D
Q
Q
D
D
Q
EXP[2:0]
A/B
REGISTER
REGISTER
INT DATA STROBE
Q
CLK
CLK
ENB
S
D
1
MULTIPLEXER
SET
Q
D
S
2
C
Q
CLR
DUAL CHANNEL REAL
SINGLE CHANNEL COMPLEX
Figure 27. Simplified Input Data Port Schematic for the AD6620
–17–
REV. A
ADI [ ADI ]
