欢迎访问ic37.com |
会员登录 免费注册
发布采购

AD6620ASZ 参数 Datasheet PDF下载

AD6620ASZ图片预览
型号: AD6620ASZ
PDF下载: 下载PDF文件 查看货源
内容描述: 67 MSPS数字接收信号处理器 [67 MSPS Digital Receive Signal Processor]
分类和应用:
文件页数/大小: 44 页 / 374 K
品牌: ADI [ ADI ]
 浏览型号AD6620ASZ的Datasheet PDF文件第11页浏览型号AD6620ASZ的Datasheet PDF文件第12页浏览型号AD6620ASZ的Datasheet PDF文件第13页浏览型号AD6620ASZ的Datasheet PDF文件第14页浏览型号AD6620ASZ的Datasheet PDF文件第16页浏览型号AD6620ASZ的Datasheet PDF文件第17页浏览型号AD6620ASZ的Datasheet PDF文件第18页浏览型号AD6620ASZ的Datasheet PDF文件第19页  
AD6620  
INPUT DATA PORT  
Thus for fixed-point ADCs, the exponents are typically static  
and no input scaling is used in the AD6620.  
The input data port accepts a clock (CLK), a 16-bit mantissa  
IN[15:0], a 3-bit exponent EXP[2:0], and channel select Pin A/B.  
These pins allow direct interfacing to both standard fixed-point  
ADCs such as the AD9225 and AD6640, as well as to gain-  
ranging ADCs such as the AD6600. These inputs are not 5 V  
tolerant and the ADC I/O should be set to 3.3 V.  
D11 (MSB)  
IN15  
AD6640  
The input data port accepts data in one of three input modes:  
Single Channel Real, Diversity Channel Real, or Single Channel  
Complex. The input mode is selected by programming the Input  
Mode Control Register located at internal address space 300h.  
AD6620  
D0 (LSB)  
IN4  
Single Channel Real mode is used when a single channel ADC  
drives the input to the AD6620. Diversity Channel Real mode is  
the two channel mode used primarily for diversity receiver appli-  
cations. Single Channel Complex mode accepts complex data in  
conjunction with the A/B input which identifies in-phase and  
quadrature samples (primarily for cascaded 6620s).  
IN3  
IN2  
IN1  
IN0  
EXP2  
EXP1  
EXP0  
A/B  
+3.3V  
The input data port is sampled on the rising edge of CLK at a  
maximum rate of 67 MSPS. The 16-bit mantissa, IN[15:0] is  
interpreted as a twos complement integer. For most applications  
with ADCs having fewer than 16 bits, the active bits should be  
MSB justified and the unused LSBs should be tied low.  
Figure 21. Typical Interconnection of the AD6640 Fixed  
Point ADC and the AD6620  
Scaling with Floating-Point ADCs  
An example of the exponent control feature combines the AD6600  
and the AD6620. The AD6600 is an 11-bit ADC with three bits  
of gain ranging. In effect, the 11-bit ADC provides the mantissa,  
and the three bits of relative signal strength indicator (RSSI) are  
the exponent. Only five of the eight available steps are used by  
the AD6600. See the AD6600 data sheet for additional details.  
The 3-bit exponent, EXP[2:0] is interpreted as an unsigned  
integer. The exponent can be modified by the 3-bit exponent  
offset ExpOff (Control Register 0x305, Bits (7–5)) and an expo-  
nent invert ExpInv (Control Register 0x305, Bit 4).  
ExpOff sets the offset of the input exponent, EXP[2:0]. ExpInv  
determines the direction of this offset. Equations below show  
how the exponent is handled.  
For gain-ranging ADCs such as the AD6600,  
scaled _input = IN ×2mod(7Exp+ExpOff,8), ExpInv =1  
scaled _input = IN ×2mod(Exp+ExpOff,8), ExpInv = 0  
scaled _input = IN ×2mod(7Exp+ExpOff,8), ExpInv =1  
where: IN is the value of IN[15:0], Exp is the value of EXP[2:0],  
and ExpOff is the value of ExpOff.  
The RSSI output of the AD6600 numerically grows with increas-  
ing signal strength of the analog input (RSSI = 5 for a large  
signal, RSSI = 0 for a small signal). With the Exponent Offset  
equal to zero and the Exponent Invert Bit equal to zero, the  
AD6620 would consider the smallest signal at the parallel input  
(EXP = 0) the largest and, as the signal and EXP word increase,  
it shifts the data down internally (EXP = 5, will shift the 11-bit  
data right by 5 bits internally before going into the CIC2). The  
AD6620 regards the largest signal possible on the AD6600 as  
the smallest signal. Thus the Exponent Invert Bit is used to make  
the AD6620 exponent agree with the AD6600 RSSI. When it  
is set high, it forces the AD6620 to shift the data up for growing  
EXP instead of down. The exponent invert bit should always be  
set high for use with the AD6600.  
where: IN is the value of IN[15:0], Exp is the value of EXP[2:0],  
and ExpOff is the value of ExpOff.  
Input Scaling  
In general there are two reasons for scaling digital data. The  
first is to avoid clippingor, in the case of the AD6620 regis-  
ter, wrap-aroundin subsequent stages. Wrap-around is not a  
concern for the input data since the NCO is designed to accept  
the largest possible input at the AD6620 data port.  
The second use of scaling is to preserve maximum dynamic  
range through the chip. As data flows from one stage to the next  
it is important to keep the math functions performed in the  
MSBs. This will keep the desired signal as far above the noise  
floor as possible, thus maximizing signal-to-noise ratio.  
Table I. AD6600 Transfer Function with AD6620 ExpInv = 1,  
and No ExpOff  
Scaling with Fixed-Point ADCs  
For fixed-point ADCs, the AD6620 exponent inputs EXP[2:0]  
are typically not used and should be tied low. The ADC outputs  
are tied directly to the AD6620 Inputs, MSB-justified. The  
exponent offset (ExpOff) and exponent invert (ExpInv) should  
both be programmed to 0. Thus the input equation,  
ADC Input  
Level  
AD6600  
RSSI[2.0]  
AD6620  
Data  
Signal  
Reduction  
Largest  
101 (5)  
100 (4)  
011 (3)  
010 (2)  
001 (1)  
000 (0)  
Ϭ 4 (>> 2)  
Ϭ 8 (>> 3)  
Ϭ 16 (>> 4)  
Ϭ 32 (>> 5)  
Ϭ 64 (>> 6)  
Ϭ 128 (>> 7)  
12 dB  
18 dB  
24 dB  
30 dB  
36 dB  
42 dB  
scaled _input = IN ×2mod(Exp+ExpOff,8), ExpInv = 0  
where: IN is the value of IN[15:0], Exp is the value of EXP[0:2],  
and ExpOff is the value of ExpOff, simplifies to,  
Smallest  
scaled _input = IN × 2mod(0, 8)  
(ExpInv = 1, ExpOff = 0)  
REV. A  
–15–  
 复制成功!