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AD6600AST 参数 Datasheet PDF下载

AD6600AST图片预览
型号: AD6600AST
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道,增益范围调整ADC ,带有RSSI [Dual Channel, Gain-Ranging ADC with RSSI]
分类和应用: 转换器模数转换器
文件页数/大小: 24 页 / 305 K
品牌: AD [ ANALOG DEVICES ]
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AD6600
TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS
1
(AVCC = 5 V, DVCC = 3.3 V; ENC and
ENC
= 20 MSPS; T
MIN
= –40 C, T
MAX
= +85 C unless otherwise noted.)
Parameter
A/D CONVERTER
Conversion Rate
Maximum Conversion Rate
Minimum Conversion Rate
Aperture Uncertainty
ENCODE INPUTS (ENC,
ENC)
2
Period
Pulsewidth High
3
Pulsewidth Low
4
2× CLOCK OUTPUT (CLK2×)
5
Output Frequency
Output Period
6
CLK2× Pulsewidth Low
6
Output Risetime
7
Output Falltime
7
OUTPUT RISE/FALL TIMES
8
Output Risetime (D10:D0, RSSI2:0)
Output Falltime (D10:D0, RSSI2:0)
Output Risetime (AB_OUT)
Output Falltime (AB_OUT)
Name
f
ENC
t
j
t
ENC
t
ENCH
t
ENCL
Full
Full
25°C
Full
Full
Full
II
IV
V
II
IV
IV
20
6
0.3
50
20
20
2× f
ENC
t
ENCL
t
ENCH
t
ENCH
/2
3
2.6
8
8.4
6
6.2
Temp
Test
Level
Min
AD6600AST
Typ
1/(t
ENC
)
Max
Unit
MSPS
MSPS
MSPS
ps rms
ns
ns
ns
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CLK2×_1
t
CLK2×_2
t
CLK2×L
Full
Full
Full
Full
Full
Full
Full
Full
Full
V
V
V
V
V
V
V
V
V
NOTES
1
See AD6600 Timing Diagrams.
2
All switching specifications tested by driving ENC and
ENC
differentially.
3
Several timing specifications are a function of Encode high time, t
ENCH
; these specifications are shown in the data tables and timing diagrams. Encode duty cycle
should be kept as close to 50% as possible.
4
Encode pulse low directly affects the amount of settling time available at FLT resonant port. See External Analog (Resonant) Filter section for details.
5
The 2× Clock is generated internally, therefore some specifications are functions of encode period and duty cycle. All timing measurements to or from CLK2
×
are
referenced to 2.0 V crossing.
6
This specification IS a function of Encode period and duty cycle; reference timing diagrams Figure 8.
7
Output rise time is measured from 20% point to 80% point of total CLK2
×
voltage swing; output fall time is measured from 80% point to 20% point of total CLK2
×
voltage swing.
8
Output rise time is measured from 20% point to 80% point of total data voltage swing; output fall time is measured from 80% point to 20% point of total data voltage
swing. All outputs specified with 10 pF load.
Specifications subject to change without notice.
REV. 0
–3–