AD6600–SPECIFICATIONS
DC SPECIFICATIONS
(AVCC = 5 V, DVCC = 3.3 V; T
Parameter
ANALOG INPUTS (AIN,
AIN/BIN, BIN)
Differential Analog Input Voltage Range
1
Differential Analog Input Resistance
2
Differential Analog Input Capacitance
PEAK DETECTOR (Internal), RSSI
Resolution
RSSI Gain Step
RSSI Hysteresis
3
RESONANT PORT (FLT,
FLT)
Differential Port Resistance
Differential Port Capacitance
A/D CONVERTER
Resolution
ENCODE INPUTS (ENC,
ENC)
Differential Input Voltage (AC-Coupled)
4
Differential Input Resistance
Differential Input Capacitance
A/B MODE INPUTS (A_SEL, B_SEL)
5
Input High Voltage Range
Input Low Voltage Range
POWER SUPPLY
Supply Voltages
AVCC
DVCC
Supply Current
I
AVCC
(AVCC = 5.0 V)
I
DVCC
(DVCC = 3.3 V)
POWER CONSUMPTION
6
Temp
Full
Full
25°C
MIN
= –40 C, T
MAX
= +85 C unless otherwise noted.)
Test
Level
V
IV
V
Min
AD6600AST
Typ
2.0
200
1.5
3
6
6
630
1.75
11
0.4
11
2.5
4.75
0.0
5.25
0.5
Max
Unit
V p-p
Ω
pF
Bits
dB
dB
Ω
pF
Bits
V p-p
kΩ
pF
V
V
160
240
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
V
V
V
V
IV
IV
V
V
IV
IV
Full
Full
Full
Full
Full
II
IV
II
II
II
4.75
3.0
5.0
3.3
145
15
775
5.25
5.25
182
20
976
V
V
mA
mA
mW
NOTES
1
Analog Input Range is a function of input frequency. See ac specifications for 70 MHz–250 MHz inputs.
2
Analog Input Impedance is a function of input frequency. See ac specifications for 70 MHz–450 MHz inputs.
3
Six dB of digital hysteresis is used to eliminate level uncertainty at the RSSI threshold points due to noise and amplitude variations.
4
Encode inputs should be ac-coupled and driven differentially. See Encoding the AD6600 for details.
5
A_SEL and B_SEL should be tied directly to ground or AVCC.
6
Maximum power consumption is computed as maximum current at nominal supplies.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(AVCC = 5 V, DVCC = 3.3 V; T
Parameter
Temp
LOGIC OUTPUTS (D10–D0, AB_OUT, RSSI2–0)
1
Logic Compatibility
Logic “1” Voltage (DVCC = 3.3 V)
Full
Logic “0” Voltage (DVCC = 3.3 V)
Full
Logic “1” Voltage (DVCC = 5.0 V)
Full
Logic “0” Voltage (DVCC = 5.0 V)
Full
Output Coding (D10–D0)
CLK2× OUTPUT
1, 2
Logic “1” Voltage (DVCC = 3.3 V)
Logic “0” Voltage (DVCC = 3.3 V)
Logic “1” Voltage (DVCC = 5.0 V)
Logic “0” Voltage (DVCC = 5.0 V)
Full
Full
Full
Full
MIN
= –40 C, T
MAX
= +85 C unless otherwise noted.)
Min
AD6600AST
Typ
CMOS
DVCC – 0.2
0.2
DVCC – 0.35
0.35
Two’s Complement
DVCC – 0.2
0.2
DVCC – 0.3
0.35
Max
Unit
Test
Level
II
II
IV
IV
2.8
4.0
0.5
0.5
V
V
V
V
II
II
IV
IV
2.8
4.0
0.5
0.5
V
V
V
V
NOTES
1
Digital output load is one LCX gate.
2
CLK2× output voltage levels, high and low, tested at switching rate of 10 MHz.
Specifications subject to change without notice.
–2–
REV. 0
AD [ ANALOG DEVICES ]
