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AD565AJD 参数 Datasheet PDF下载

AD565AJD图片预览
型号: AD565AJD
PDF下载: 下载PDF文件 查看货源
内容描述: 高速12位单片D / A转换器 [High Speed 12-Bit Monolithic D/A Converters]
分类和应用: 转换器
文件页数/大小: 11 页 / 154 K
品牌: ADI [ ADI ]
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AD565A/AD566A  
AD566AS  
Typ  
AD566AT  
Typ  
Model  
Min  
Max  
Min  
Max  
Units  
DATA INPUTS1 (Pins 13 to 24)  
TTL or 5 Volt CMOS  
Input Voltage  
Bit ON Logic “1”  
+2.0  
0
+5.5  
+0.8  
+2.0  
0
+5.5  
+0.8  
V
V
Bit OFF Logic “0”  
Logic Current (Each Bit)  
Bit ON Logic “1”  
+120  
+35  
+300  
+100  
+120  
+35  
+300  
+100  
µA  
µA  
Bit OFF Logic “0”  
RESOLUTION  
12  
12  
Bits  
OUTPUT  
Current  
Unipolar (All Bits On)  
Bipolar (All Bits On or Off)  
Resistance (Exclusive of Span Resistors)  
Offset  
–1.6  
؎0.8  
6
–2.0  
1.0  
8
–2.4  
؎1.2  
10  
–1.6  
؎0.8  
6
–2.0  
1.0  
8
–2.4  
؎1.2  
10  
mA  
mA  
kΩ  
Unipolar (Adjustable to Zero per Figure 3)  
Bipolar (Figure 4, R1 and R2 = 50 Fixed)  
Capacitance  
Compliance Voltage  
TMIN to TMAX  
0.01  
0.05  
25  
0.05  
0.15  
0.01  
0.05  
25  
0.05  
0.1  
% of F.S. Range  
% of F.S. Range  
pF  
–1.5  
+10  
–1.5  
+10  
V
ACCURACY (Error Relative to  
Full Scale) +25°C  
1/4  
؎1/2  
1/8  
؎1/4  
LSB  
(0.006)  
1/2  
(0.012)  
؎3/4  
(0.003)  
1/4  
(0.006)  
؎1/2  
% of F.S. Range  
LSB  
T
MIN to TMAX  
(0.012)  
(0.018)  
(0.006)  
(0.012)  
% of F.S. Range  
DIFFERENTIAL NONLINEARITY  
+25°C  
1/2  
؎3/4  
1/4  
؎1/2  
LSB  
TMIN to TMAX  
MONOTONICITY GUARANTEED  
MONOTONICITY GUARANTEED  
TEMPERATURE COEFFICIENTS  
Unipolar Zero  
1
5
7
2
2
10  
10  
1
5
3
2
2
10  
5
ppm/°C  
ppm/°C  
ppm/°C  
ppm/°C  
Bipolar Zero  
Gain (Full Scale)  
Differential Nonlinearity  
SETTLING TIME TO 1/2 LSB  
All Bits ON-to-OFF or OFF-to-ON (Figure 8)  
250  
350  
250  
350  
ns  
FULL-SCALE TRANSITION  
10% to 90% Delay plus Rise Time  
90% to 10% Delay plus Fall Time  
15  
30  
30  
50  
15  
30  
30  
50  
ns  
ns  
POWER REQUIREMENTS  
VEE, –11.4 to –16.5 V dc  
POWER SUPPLY GAIN SENSITIVITY2  
VEE = –11.4 to –16.5 V dc  
–12  
15  
–18  
25  
–12  
15  
–18  
25  
mA  
ppm of F.S./%  
PROGRAMMABLE OUTPUT RANGES  
(see Figures 3, 4, 5)  
0 to +5  
0 to +5  
V
V
V
V
V
–2.5 to +2.5  
0 to +10  
–2.5 to +2.5  
0 to +10  
–5 to +5  
–10 to +10  
–5 to +5  
–10 to +10  
EXTERNAL ADJUSTMENTS  
Gain Error with Fixed 50 Ω  
Resistor for R2 (Figure 3)  
Bipolar Zero Error with Fixed  
50 Resistor for R1 (Figure 4)  
Gain Adjustment Range (Figure 3)  
Bipolar Zero Adjustment Range  
0.1  
؎0.25  
؎0.15  
0.1  
؎0.25  
؎0.1  
% of F.S. Range  
0.05  
0.05  
% of F.S. Range  
% of F.S. Range  
% of F.S. Range  
0.25  
0.15  
0.25  
0.15  
REFERENCE INPUT  
Input Impedance  
15  
20  
25  
15  
20  
25  
kΩ  
POWER DISSIPATION  
180  
300  
180  
300  
mW  
MULTIPLYING MODE PERFORMANCE (All Models)  
Quadrants  
Two (2): Bipolar Operation at Digital Input Only  
+1 V to +10 V, Unipolar  
10 Bits ( 0.05% of Reduced F.S.) for 1 V dc Reference Voltage  
Reference Voltage  
Accuracy  
Reference Feedthrough (Unipolar Mode,  
All Bits OFF, and 1 V to +10 V [p-p], Sine Wave  
Frequency for l/2 LSB [p-p] Feedthrough)  
Output Slew Rate 10%–90%  
40 kHz typ  
5 mA/µs  
90%–10%  
1 mA/µs  
Output Settling Time (All Bits ON and a 0 V–10 V  
Step Change in Reference Voltage)  
1.5 µs to 0.01% F.S.  
CONTROL AMPLIFIER  
Full Power Bandwidth  
300 kHz  
1.8 MHz  
Small-Signal Closed-Loop Bandwidth  
NOTES  
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max  
specifications are guaranteed, although only those shown in boldface are tested on all production units.  
Specification subject to change without notice.  
REV. D  
–5–