AD538
TWO-QUADRANT DIVISION
LOG RATIO OPERATION
The two-quadrant linear divider circuit illustrated in Figure 13
uses the same basic connections as the one-quadrant version.
However, in this circuit the numerator has been offset in the
positive direction by adding the denominator input voltage to it.
The offsetting scheme changes the divider’s transfer function
from:
V
V
O
=
10V
Z
V
X
to:
Figure 14 shows the AD538 configured for computing the log of
the ratio of two input voltages (or currents). The output signal
from B is connected to the summing junction of the output ampli-
fier via two series resistors. The 90.9
Ω
metal film resistor effec-
tively degrades the temperature coefficient of the
±
3500 ppm/°C
resistor to produce a 1.09 kΩ +3300 ppm/°C equivalent value.
In this configuration, the V
Y
input must be tied to some voltage
less than zero (–1.2 V in this case) removing this input from the
transfer function.
The 5 kΩ potentiometer controls the circuit’s scale factor ad-
justment providing a +1 V per decade adjustment. The output
offset potentiometer should be set to provide a zero output with
V
X
= V
Z
= 1 V. The input V
Z
adjustment should be set for an
output of 3 V with V
Z
= l mV and V
X
= 1 V.
–V
S
68k
5%
–1.2V
10M
1M
OPTIONAL
INPUT V
OS
ADJUSTMENT
90.9
1%
1k
+3500
ppm/ C
OUTPUT
I
Z
V
Z
B
+10V
+2V
V
O
= 1V LOG
10
V
O
=
10V
(
V
Z
+
AV
X
V
X
)
V
Z
=
10
V
1
A
+
V
X
V
Z
=
10
A
+
10
V
V
X
AD589
(
V
Z
)
V
X
35
kΩ
where
A
=
25
kΩ
As long as the magnitude of the denominator input is equal to
or greater than the magnitude of the numerator input, the cir-
cuit will accept bipolar numerator voltages. However, under the
conditions of a 0 V numerator input, the output would incor-
rectly equal +14 V. The offset can be removed by connecting
the +10 V reference through resistors R1 and R2 to the output
section’s summing node I at Pin 9 thus providing a gain of 1.4
at the center of the trimming potentiometer. The pot R2 adjusts
out or corrects this offset, leaving the desired transfer function
of 10 V (V
Z
/ V
X
).
OPTIONAL
Z OFFSET TRIM
–V
S
V
OUT
= 10
1
18
A
D
25k
2
3
4
LOG
RATIO
48.7
17
16
I
X
15
14
V
X
V
X
INPUT
100
5
100
25k
SIGNAL
GND
PWR
GND
C
I
Y
V
Y
IN4148
+15V
6
INTERNAL
VOLTAGE
REFERENCE
OUTPUT
25k
AD538
13
12
11
10
5k
SCALE
FACTOR
ADJUST
2k
1%
–15V
7
V
O
I
8
9
ANTILOG
LOG
25k
NUMERATOR
V
Z
DENOMINATOR
V
X
+V
S
10M
10k
–V
S
OPTIONAL
OUTPUT V
OS
ADJUSTMENT
AD589
1M
V
OS
ADJ
68k
5%
–1.2V
10M
35k
(
V
Z
)
V
X
V
X
FOR
V
Z
Figure 14. Log Ratio Circuit
1
18
A
I
Z
V
Z
B
+10V
3.9M
25k
2
3
4
LOG
RATIO
35k
17
D
16
I
X
100
+2V
5
+15V
–15V
OUTPUT
V
O
6
7
8
9
100
25k
INTERNAL
VOLTAGE
REFERENCE
OUTPUT
25k
AD538
15
V
X
SIGNAL
GND
14
PWR
GND
13
IN4148
C
12
11
10
The log ratio circuit shown achieves
±0.5%
accuracy in the log
domain for input voltages within three decades of input range:
10 mV to 10 V. This error is not defined as a percent of full-
scale output, but as a percent of input. For example, using a
1 V/decade scale factor, a 1% error in the positive direction at
the INPUT of the log ratio amplifier translates into a 4.3 mV
deviation from the ideal OUTPUT (i.e., 1 V
×
log
10
(1.01) =
4.3214 mV). An input error 1% in the negative direction is
slightly different, giving an output deviation of 4.3648 mV.
I
Y
V
Y
R2
10k
R1
12.4k
ANTILOG
LOG
25k
I
ZERO
ADJUST
Figure 13. Two-Quadrant Division with 10 V Scaling
–8–
REV. C
AD [ ANALOG DEVICES ]
