AD538
STABILITY PRECAUTIONS
ONE-QUADRANT MULTIPLICATION/DIVISION
At higher frequencies, the multistaged signal path of the AD538,
as illustrated in Figure 10, can result in large phase shifts. If a
condition of high incremental gain exists along that path (e.g.,
V
O
= V
Y
×
V
Z
/ V
X
= 10 V
×
10 mV/10 mV = 10 V so that
∆V
O
/∆V
X
= 1000), then small amounts of capacitive feedback
from V
O
to the current inputs I
Z
or I
X
can result in instability.
Appropriate care should be exercised in board layout to pre-
vent capacitive feedback mechanisms under these conditions.
I
X
LOG
e
V
X
–
0.2 M 5
+
I
Z
LOG
e
V
Z
Ln Z
I
Y
LOG
e
V
Y
Ln Y
+
ANTILOG
e
+
V
Z
V
O
= V
Y
V
X
M
Figure 12 shows how the AD538 may be easily configured as a
precision one-quadrant multiplier/divider. The transfer function
V
OUT
= V
Y
(V
Z
/V
X
) allows “three” independent input variables,
a calculation not available with a conventional multiplier. In
addition, the 1000:1 (i.e., 10 mV to 10 V) input dynamic range
of the AD538 greatly exceeds that of analog multipliers comput-
ing one-quadrant multiplication and division.
V
OUT
= V
Y
(
V
Z
)
V
X
18
A
Ln Z – Ln X
Ln X
M(Ln Z – Ln X)
M(Ln Z – Ln X) +Ln Y
V
Z
INPUT
I
Z 1
V
Z
25k
2
BUFFER
LOG
RATIO
17
D
B
3
16
I
X
+10V
4
100
+2V
5
6
15
V
X
SIGNAL
GND
PWR
GND
C
I
Y
V
Y
IN4148
100
25k
14
V
X
INPUT
Figure 10. Model Circuit
USING THE VOLTAGE REFERENCES
+15V
INTERNAL
VOLTAGE
REFERENCE
OUTPUT
25k
AD538
13
A stable bandgap voltage reference for scaling is included in the
AD538. It is laser-trimmed to provide a selectable voltage out-
put of +10 V buffered (Pin 4), +2 V unbuffered (Pin 5) or any
voltages between +2 V and +10.2 V buffered as shown in Figure
11. The output impedance at Pin 5 is approximately 5 kΩ. Note
that any loading of this pin will produce an error in the +10 V
reference voltage. External loads on the +2 V output should be
greater than 500 kΩ to maintain errors less than 1%.
–15V
V
O
OUTPUT
I
7
12
8
11
ANTILOG
9
LOG
10
25k
V
Y
INPUT
Figure 12. One-Quadrant Combination Multiplier/Divider
I
Z 1
+2V TO +10.2V
BUFFERED
V
Z 2
B
3
REF OUT
+2V
25k
LOG
RATIO
18
A
17
D
By simply connecting the input V
X
(Pin 15) to the +10 V refer-
ence (Pin 4), and tying the log-ratio output at B to the antilog
input at C, the AD538 can be configured as a one-quadrant
analog multiplier with 10-volt scaling. If 2-volt scaling is desired,
V
X
can be tied to the +2 V reference.
When the input V
X
is tied to the +10 V reference terminal, the
multiplier transfer function becomes:
V
V
O
=
V
Y
Z
10
V
As a multiplier, this circuit provides a typical bandwidth of
400 kHz with values of V
X
, V
Y
or V
Z
varying over a 100:1 range
(i.e., 100 mV to 10 V). The maximum error with a 100 mV to
10 V range for the two input variables will typically be +0.5% of
reading. Using the optional Z offset trim scheme, as shown in
Figure 13, this error can be reduced to +0.25% of reading.
By using the +10 V reference as the V
Y
input, the circuit of
Figure 12 is configured as a one-quadrant divider with a fixed
scale factor. As with the one-quadrant multiplier, the inputs
accept only single (positive) polarity signals. The output of the
one-quadrant divider with a +10 V scale factor is:
V
V
O
=
10V
Z
V
X
The typical bandwidth of this circuit is 370 kHz with 1 V to
10 V denominator input levels. At lower amplitudes, the band-
width gradually decreases to approximately 200 kHz at the
2 mV input level.
16
I
X
4
100
50k
11.5k
5
100
25k
15
V
X
14
SIGNAL
GND
PWR
GND
+V
S 6
–V
S 7
V
O 8
I
9
INTERNAL
VOLTAGE
REFERENCE
OUTPUT
25k
ANTILOG
AD538
13
12
C
11
I
Y
LOG
25k
10
V
Y
Figure 11. +2 V to +10.2 V Adjustable Reference
In situations not requiring both reference levels, the +2 V output
can be converted to a buffered output by tying Pins 4 and 5
together. If both references are required simultaneously, the
+10 V output should be used directly and the +2 V output
should be externally buffered.
REV. C
–7–
AD [ ANALOG DEVICES ]
