AD5382
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
98
DB12/(SCLK/SCL)
100
CS/(SYNC/AD0)
99
DB13/(DIN/SDA)
78
WR (DCEN/AD1)
97
DB11/(SPI/I2C)
93
SDO(A/B)
92
DVDD
80
SER/PAR
91
DGND
90
DGND
81
DGND
84
A0
83
DVDD
82
DVDD
76
BUSY
77
LDAC
96
DB10
95
DB9
94
DB8
89
NC
88
A4
FIFO EN
CLR
VOUT24
VOUT25
VOUT26
VOUT27
SIGNAL_GND4
DAC_GND4
AGND4
AVDD4
VOUT28
VOUT29
VOUT30
VOUT31
REF GND
REFOUT/REFIN
SIGNAL_GND1
DAC_GND1
AVDD1
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
AGND1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN 1
IDENTIFIER
79
PD
87
A3
86
A2
85
A1
75
RESET
74
DB7
73
DB6
72
DB5
71
DB4
70
DB3
69
DB2
68
DB1
67
DB0
66
REG0
65
REG1
AD5382
TOP VIEW
(Not to Scale)
64
VOUT23
63
VOUT22
62
VOUT21
61
VOUT20
60
AVDD3
59
AGND3
58
DAC_GND3
57
SIGNAL_GND3
56
VOUT19
55
VOUT18
54
VOUT17
53
VOUT16
52
AVDD2
51
AGND2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
NC
NC
NC
NC
VOUT5
VOUT6
VOUT7
NC
NC
MON_IN1
MON_IN2
MON_IN3
MON_IN4
NC
MON_OUT
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
DAC_GND2
SIGNAL_GND2
VOUT13
VOUT14
VOUT15
50
Figure 8. 100-Lead LQFP Pin Configuration
Table 10. Pin Function Descriptions
Mnemonic
VOUTx
SIGNAL_GND(1–4)
DAC_GND(1–4)
AGND(1–4)
AVDD(1–4)
Function
Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a
gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω.
Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together
internally and should be connected to the AGND plane as close as possible to the AD5382.
Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit
DAC. These pins shound be connected to the AGND plane.
Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be
connected externally to the AGND plane.
Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are internally shorted and
should be decoupled with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor. Operating range for the
AD5382-5 is 4.5 V to 5.5 V; operating range for the AD5382-3 is 2.7 V to 3.6 V.
Ground for All Digital Circuitry.
Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled
with 0.1 µF ceramic and 10 µF tantalum capacitors to DGND.
Ground Reference Point for the Internal Reference.
The AD5382 contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference
output. If the application requires an external reference, it can be applied to this pin and the internal reference can
be disabled via the control register. The default for this pin is a reference input.
When the monitor function is enabled, this pin acts as the output of a 36-to-1 channel multiplexer that can be
programmed to multiplex one of channels 0 to 31 or any of the monitor input pins (MON_IN1 to MON_IN4) to the
MON_OUT pin. The MON_OUT pin’s output impedance is typically 500 Ω and is intended to drive a high input
impedance like that exhibited by SAR ADC inputs.
Rev. 0 | Page 14 of 40
DGND
DVDD
REFGND
REFOUT/REFIN
MON_OUT
03733-0-002
AD [ ANALOG DEVICES ]
