AD5382
PARALLEL INTERFACE
Table 8. DV
DD
= 2.7 V to 5.5 V; AV
DD
= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
T
MIN
to T
MAX
, unless otherwise noted
Parameter
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
94
t
104
t
114, 5
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
Limit at T
MIN
, T
MAX
4.5
4.5
20
20
0
0
4.5
4.5
20
700
30
670
30
20
100
20
0
100
8
20
35
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns min
µs typ
ns min
µsmax
Description
REG0, REG1, address to WR rising edge setup time
REG0, REG1, address to WR rising edge hold time
CS pulse width low
WR pulse width low
CS to WR falling edge setup time
WR to CS rising edge hold time
Data to WR rising edge setup time
Data to WR rising edge hold time
WR pulse width high
Minimum WR cycle time (single-channel write)
WR rising edge to BUSY falling edge
BUSY pulse width low (single-channel update)
WR rising edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
LDAC rising edge to WR rising edge
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
1
2
Guaranteed by design and characterization, not production tested.
All input signals are specified with t
R
= t
R
= 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.2 V.
3
See Figure 7.
4
See Figure 29.
5
Measured with the load circuit of Figure 2.
Rev. 0 | Page 11 of 40
AD [ ANALOG DEVICES ]
