AD5382
TIMING CHARACTERISTICS
SPI, QSPI, MICROWIRE, OR DSP COMPATIBLE SERIAL INTERFACE
Table 6. DV
DD
= 2.7 V to 5.5 V ; AV
DD
= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
T
MIN
to T
MAX
, unless otherwise noted
Parameter
t
1
t
2
t
3
t
4
t
5 4
t
6 4
t
7
t
7A
t
8
t
9
t
104
t
11
t
12 4
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20 5
t
215
t
225
t
23
Limit at T
MIN
, T
MAX
33
13
13
13
13
33
10
50
5
4.5
30
670
20
20
100
0
100
8
20
35
20
5
8
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
µs typ
ns min
µs max
ns max
ns min
ns min
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC falling edge
Minimum SYNC low time
Minimum SYNC high time
Minimum SYNC high time in Readback mode
Data setup time
Data hold time
24th SCLK falling edge to BUSY falling edge
BUSY pulse width low (single channel update)
24th SCLK falling edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
1
2
Guaranteed by design and characterization, not production tested.
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of V
CC
) and are timed from a voltage level of 1.2 V.
3
See Figure 2, Figure 3, Figure 4, and Figure 5.
4
Standalone mode only.
5
Daisy-chain mode only.
200µA
I
OL
TO OUTPUT PIN
C
L
50pF
200µA
I
OH
V
OH
(MIN) OR
V
OL
(MAX)
03731-0-003
Figure 2. Load Circuit for SDO Timing Diagram
(Serial Interface, Daisy-Chain Mode)
Rev. 0 | Page 8 of 40
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