AD5382
Parameter
LOGIC OUTPUTS (BUSY, SDO)
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
High Impedance Leakage Current
High Impedance Output Capacitance
LOGIC OUTPUT (SDA)
V
OL
, Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
AV
DD
DV
DD
Power Supply Sensitivity
∆Midscale/∆ΑV
DD
AI
DD
DI
DD
AI
DD
(Power-Down)
DI
DD
(Power-Down)
Power Dissipation
AD5382-3
1
0.4
DV
DD
– 0.5
±1
5
0.4
0.6
±1
8
2.7/3.6
2.7/5.5
–85
0.375
0.475
1
2
20
39
Unit
V max
V min
µA max
pF typ
V max
V max
µA max
pF typ
V min/max
V min/max
dB typ
mA/channel max
mA/channel max
mA max
µA max
µA max
mW max
Test Conditions/Comments
Sinking 200 µA
Sourcing 200 µA
SDO only
SDO only
I
SINK
= 3 mA
I
SINK
= 6 mA
Outputs unloaded, Boost off. 0.25 mA/channel typ
Outputs unloaded, Boost on. 0.325 mA/channel typ
V
IH
= DV
DD
, V
IL
= DGND.
Outputs unloaded, Boost off, AV
DD
= DV
DD
= 3 V
1
2
AD5382-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C.
Accuracy guaranteed from V
OUT
= 10 mV to AV
DD
– 50 mV.
3
Guaranteed by characterization, not production tested.
4
Default on the AD5382-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5382 control register; operating the AD5382-5 with a 1.25 V reference leads to degraded
accuracy specifications.
AC CHARACTERISTICS
Table 5. AV
DD
= 4.5 V to 5.5 V; DV
DD
= 2.7 V to 5.5 V; AGND = DGND= 0 V
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
All
Unit
Test Conditions/Comments
1/4 scale to 3/4 scale change settling to ±1 LSB.
8
10
2
3
12
15
100
1
0.8
0.1
15
40
150
100
µs typ
µs max
V/µs typ
V/µs typ
nV-s typ
mV typ
dB typ
nV-s typ
nV-s typ
nV-s typ
µV p-p typ
µV p-p typ
nV/√Hz typ
nV/√Hz typ
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise 0.1 Hz to 10 Hz
Output Noise Spectral Density
@ 1 kHz
@ 10 kHz
Boost mode off, CR11 = 0
Boost mode on, CR11 = 1
See Terminology section
See Terminology section
Effect of input bus activity on DAC output under test
External reference, midscale loaded to DAC
Internal reference, midscale loaded to DAC
1
2
Guaranteed by design and characterization, not production tested.
The slew rate can be programmed via the current boost control bit (CR11 ) in the AD5382 control register.
Rev. 0 | Page 7 of 40
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