AD2S81A/AD2S82A
BUSY
V
H
t
1
RIPPLE
CLK
V
H
CIRCUIT FUNCTIONS AND DYNAMIC
PERFORMANCE
V
L
t
2
V
H
t
4
DATA
V
H
V
H
V
L
V
L
t
3
t
5
INHIBIT
V
H
t
6
V
H
DIR
The AD2S81A/AD2S82A allows the user greater flexibility in
choosing the dynamic characteristics of the resolver-to-digital
conversion to ensure the optimum system performance. The
characteristics are set by the external components shown in
Figure 1, and the Component Selection section explains how to
select desired maximum tracking rate and bandwidth values.
The following paragraphs explain in greater detail the circuit of
the AD2S81A/AD2S82A and the variations in the dynamic
performance available to the user.
Loop Compensation
t
7
V
L
t
8
INHIBIT
V
L
V
L
V
Z
t
9
The AD2S81A and AD2S82A (connected as shown in Figure
1a and 1b) operates as a type 2 tracking servo loop where the
VCO/counter combination and integrator perform the two inte-
gration functions inherent in a type 2 loop.
V
H
ENABLE
t
10
t
11
DATA
V
L
V
H
V
H
Additional compensation in the form of a pole/zero pair is re-
quired to stabilize any type 2 loop to avoid the loop gain charac-
teristic crossing the 0 dB axis with 180° of additional phase lag,
as shown in Figure 6. This compensation is implemented by the
integrator components (R4, C4, R5, C5).
The overall response of such a system is that of a unity gain
second order low pass filter, with the angle of the resolver as the
input and the digital position data as the output.
The AD2S81A/AD2S82A does not have to be connected as
tracking converter, parts of the circuit can be used indepen-
dently. This is particularly true of the Ratio Multiplier which
can be used as a control transformer (see Application Note).
A block diagram of the AD2S81A/AD2S82A is given in
Figure 4.
BYTE
SELECT
V
L
DATA
t
12
PARAMETER
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
T
MIN
200
10
470
16
3
70
485
515
–
40
35
60
60
T
MAX
600
25
580
45
25
140
625
670
600
110
110
140
125
CONDITION
t
13
V
L
BUSY WIDTH V
H
–V
H
RIPPLE CLOCK V
H
TO BUSY V
H
RIPPLE CLOCK V
L
TO NEXT BUSY V
H
BUSY V
H
TO DATA V
H
BUSY V
H
TO DATA V
L
INHIBIT
V
H
TO BUSY V
H
MIN DIR V
H
TO BUSY V
H
MIN DIR V
H
TO BUSY V
H
INHIBIT
V
L
TO DATA STABLE
ENABLE
V
L
TO DATA V
H
ENABLE
V
L
TO DATA V
L
BYTE SELECT V
L
TO DATA STABLE
BYTE SELECT V
H
TO DATA STABLE
Figure 3. Digital Timing
R5
AC ERROR
C4
sin
cos
sin
sin
t
t
RATIO
MULTIPLIER
A1 sin ( –
) sin
PHASE-
SENSITIVE
t DEMODULATOR
R4
INTEGRATOR
C5
CLOCK
R6
DIGITAL
DIRECTION
VCO
VELOCITY
Figure 4. AD2S81A/AD2S82A Functional Diagram
–10–
REV. B
AD [ ANALOG DEVICES ]
