AD2S81A/AD2S82A
CONNECTING THE CONVERTER
The power supply voltages connected to +V
S
and –V
S
pins
should be +12 V dc and –12 V dc and must not be reversed.
The voltage applied to V
L
can be +5 V dc to +V
S
.
It is recommended that the decoupling capacitors are connected
in parallel between the power lines +V
S
, –V
S
and ANALOG GND
adjacent to the converter. Recommended values are 100 nF
(ceramic) and 10
µF
(tantalum). Also capacitors of 100 nF and
10
µF
should be connected between +V
L
and DIGITAL GND
adjacent to the converter.
When more than one converter is used on a card, then separate
decoupling capacitors should be used for each converter.
The resolver connections should be made to the SIN and
COS inputs, REFERENCE I/P and SIGNAL GND as shown
in Figure 7 and described in the Connecting the Resolver
section.
The two signal ground wires from the resolver should be joined
at the SIGNAL GROUND pin of the resolver to minimize the
coupling between the sine and cosine signals. For this reason it
is also recommended that the resolver is connected using indi-
vidually screened twisted pair cables with the sine, cosine and
reference signals twisted separately.
SIGNAL GND and ANALOG GND are connected internally.
ANALOG GND and DIGITAL GND must be connected
externally.
The external components required should be connected as
shown in Figures 1a and 1b.
REFERENCE I/P
OFFSET ADJUST
R9
–12V
+12V
R8
BANDWIDTH
SELECTION
R4
DEMOD
I/P
DEMOD
O/P
INTEGRATOR
I/P
C4
C5
R5
HP FILTER
C3
R3
C1
R1
AC ERROR
O/P
SIN I/P
SIGNAL GND
COS I/P
ANALOG GND
RIPPLE CLK
+12V
–12V
COMP
DATA SC1 SC2
LOAD
ENABLE
A1
R2
C2
SEGMENT
SWITCHING
A2
R-2R DAC
A3
PHASE-SENSITIVE
DETECTOR
INTEGRATOR
O/P
VELOCITY
SIGNAL
AD2S82A
16-BIT UP/DOWN COUNTER
OUTPUT DATA LATCH
VCO
DATA TRANSFER
LOGIC
R6
VCO I/P
R7
C6
TRACKING
RATE
SELECTION
16 DATA BITS
+5V DIGITAL BUSY VCO DIR
INHIBIT
O/P
GND
BYTE
SELECT
Figure 1a. AD2S82A Connection Diagram
REFERENCE I/P
OFFSET ADJUST
R9
–12V
+12V
R8
R4
DEMOD
I/P
DEMOD
O/P
INTEGRATOR
I/P
BANDWIDTH
SELECTION
C5
R5
HP FILTER
C3
R3
C1
R1
AC ERROR
O/P
R2
C2
C4
SIN I/P
SIGNAL GND
COS I/P
A1
PHASE-SENSITIVE
DETECTOR
SEGMENT
SWITCHING
R-2R DAC
A3
INTEGRATOR
O/P
VELOCITY
SIGNAL
A2
AD2S81A
16-BIT UP/DOWN COUNTER
OUTPUT DATA LATCH
ENABLE
8 DATA BITS
BYTE
SELECT
+5V DIGITAL
GND
VCO
DATA TRANSFER
LOGIC
R6
TRACKING
RATE
SELECTION
RIPPLE CLK
+12V
–12V
VCO I/P
R7
C6
BUSY
DIR
INHIBIT
Figure 1b. AD2S81A Connection Diagram
–6–
REV. B
AD [ ANALOG DEVICES ]
