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AD1954YSTZ 参数 Datasheet PDF下载

AD1954YSTZ图片预览
型号: AD1954YSTZ
PDF下载: 下载PDF文件 查看货源
内容描述: SigmaDSPâ ?? ¢ 3通道, 26比特信号处理DAC [SigmaDSP™ 3-Channel, 26-Bit Signal Processing DAC]
分类和应用: 消费电路商用集成电路
文件页数/大小: 36 页 / 1377 K
品牌: ADI [ ADI ]
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GENERAL DESCRIPTION
(continued from page 1)  
An extensive SPI port allows click-free parameter updates, along  
with read-back capability from any point in the algorithm flow.  
The AD1954 contains a program RAM that boots from an internal  
program ROM on power-up. Signal processing parameters are  
stored in a 256-location parameter RAM, which is initialized on  
power-up by an internal boot ROM. New values are written to  
the parameter RAM using the SPI port.The values stored in the  
parameter RAM control the IIR equalization filters, the dual-  
band compressor/limiter, the delay values, and the settings of the  
stereo spreading algorithm.  
The AD1954 includes ADI’s patented multibit
-
DAC architec-  
ture.This architecture provides 112 dB SNR and dynamic range  
andTHD+N of –100 dB.These specifications allow the AD1954  
to be used in applications ranging from low-end boom boxes to  
high-end professional mixing/editing systems.  
The AD1954 has a very sophisticated SPI port that supports  
complete read/write capability of both the program and the para-  
meter RAM.Two control registers are also provided to control  
the chip serial modes and various other optional features. Hand-  
shaking is also included for ease of memory uploads/downloads.  
The AD1954 also has a digital output that allows it to be used  
purely as a DSP.This digital output can also be used to drive an  
external DAC to extend the number of channels beyond the three  
that are provided on the chip.  
This chip can be used with either its default signal processing  
program or with a custom user-designed program. Graphical pro-  
gramming tools are available from ADI for custom programming.  
The AD1954 contains four independent data capture circuits,  
which can be programmed to tap the signal flow of the processor  
at any point in the DSP algorithm flow.These captured signals  
can be accessed either through a separate serial out pin (i.e., that  
can be connected to an external DAC or DSP) or by reading from  
the data capture SPI registers.This allows the basic functionality  
of the AD1954 to be easily extended.  
FEATURES  
The AD1954 is comprised of a 26-bit DSP (48 bits with double  
precision) for interpolation and audio processing, three multibit  
-
modulators, and analog output drive circuitry. Other features  
include an on-chip parameter RAM that uses a safe-upload feature  
for transparent and simultaneous updates of filter coefficients and  
digital de-emphasis filters. Also, on-chip input selectors allow up  
to three sources of serial data and master clock to be selected.  
The 3-channel configuration is especially useful for 2.1 playback  
systems that include two satellite speakers and a subwoofer.  
The default program allows for independent equalization and  
compression/limiting for the satellite and subwoofer outputs.  
Figure 1 shows the block diagram of the device.  
The processor core in the AD1954 has been designed from the  
ground up for straightforward coding of sophisticated compres-  
sion/limiting algorithms.The AD1954 contains two independent  
compressor/limiters with rms based amplitude detection and  
attack/hold/release controls, together with an arbitrary compression  
curve that is loaded by the user into a look-up table that resides  
in the parameter RAM.The compressor also features look-ahead  
compression that prevents compressor overshoots.  
VREF  
ZEROFLAG  
RESETB  
MUTE DE-EMPHASIS  
DVDD  
AVDD  
3
ODVDD  
VOLTAGE  
3
DATA MEMORY, 512 26  
REFERENCE  
3
DAC – L  
DAC – R  
3:1  
SERIAL DATA I/O  
GROUP  
3
3
AUDIO  
SERIAL  
IN  
ANALOG  
OUTPUTS  
26 22  
DSP CORE  
DATA  
MUX  
1
1
2
DAC – SW  
AUX SERIAL  
DATA INPUT  
DATA FORMAT:  
3.23 (SINGLE PRECISION)  
ANALOG  
BIAS GROUP  
BIAS  
3.45 (DOUBLE PRECISION)  
MCLK  
GENERATOR  
(256 fS/512 fS IN)  
256 fS/512 fS OUT  
MASTER  
CLOCK I/O  
GROUP  
3:1  
1
MCLK  
1
MUX  
CONTROL  
COEFFICIENT  
ROM  
64 22  
PROGRAM  
RAM  
512 35  
PARAMETER  
RAM  
256 22  
REGISTERS  
SPI I/O  
GROUP  
TRAP REG.  
SPI PORT  
FILTCAP  
3
2
(I S, SPI)  
SAFELOAD  
REGISTERS  
DCSOUT  
MEMORY CONTROLLERS  
DCSOUTTRAP  
AGND  
3
DGND  
2
NOTES  
1
CONTROLLEDTHROUGH SPI CONTROL REGISTERS.  
2
DAC DOES NOT USE DIGITAL INTERPOLATION.  
Figure 1. Block Diagram  
–9–  
REV. A