PIN FUNCTION DESCRIPTIONS
Input/
(44-MQFP) (48-LQFP) Mnemonic Output Description*
SDATA_AUX
Master Clock Input 2 256 fS/512 f
S
Master Clock Input 1 256 fS/512 f
S
Master Clock Input 0 256 fS/512 f
S
Enables 44.1 kHz De-emphasis Filter (Others Available through SPI Control)
Auxiliary Serial Data Input
6
DVDD
Mute Signal. Initiates volume ramp-down.
Digital Supply for DSP Core, 4.5V to 5.5V
Serial Data Input 2
Left/Right Clock 2
Serial Data Input 1
Digital Ground
Left/Right Clock 1
Serial Data Input 0
Left/Right Clock 0
SPI Data Input
LRCLK0
AGND
37
16
IN
SPI Data Framing Signal
Reset Signal, Active Low
Analog 5V Supply
Analog GND
Negative Sub Analog DAC Output
Positive Sub Analog DAC Output
Analog GND
Negative Left Analog DAC Output
Positive Left Analog DAC Output
Analog 5V Supply
Analog GND
Analog 5V Supply
Positive Left Analog DAC Output
Negative Left Analog DAC Output
Analog GND
25
No Connect
NC
Connection for Filtered
A
V
DD/2
Connection for Noise Reduction Capacitor
Zero Flag Output. High when both left and right channels are 0 for 1024 frames.
Serial Data Mux Output
Bit Clock Mux Output
Left/Right Clock Mux Output
Digital Supply Pin for Output Drivers, 2.5V to 5.5V
Data Capture Serial Output for Data Capture Registers. Use in conjunction with
selected LRCLK and BCLK to form a 3-wire output.
43
MCLKOUT OUT
SPI Data Output.Three-stated when inactive.
Master Clock Output 512 fS/256 fS (Frequency Selected by SPI Register)
Digital Ground
*
For a complete description of the pins, refer to the Pin Functions section. REV. A
ADI [ ADI ]
