MCLKOUT
—Master Clock Output The AD1954 has a very flexible serial data input port, which
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers, and sample rate converters. The
AD1954 can be configured in left-justified, I2S, right-justified, or
DSP serial port compatible modes. It can support 16 bits, 20 bits,
and 24 bits in all modes. The AD1954 accepts serial audio data
in MSB first, twos complement format. The part can also be set
up in a 4-channel serial input mode by simultaneously using the
serial input mux and the auxiliary serial input.
The master clock output pin may be programmed to produce
either 256
f
S, 512
f
S, or a copy of the selected MCLK input pin.This pin is programmed by writing to Bits 1 and 0 of Control
Register 2.The default is 00, which disables the MCLKO pin.
CDATA
—Serial Data In for the SPI Control Port
See SPI Port section for more information on SPI port timing.
The AD1954 operates from a single 5V power supply. It is fabri-
cated on a single monolithic integrated circuit and is housed in a
44-lead MQFP or 48-lead LQFP package for operation over the
temperature range –40°C to +105°C.
This is used for reading back registers and memory locations. It
is three-stated when an SPI read is not active. See SPI Port section
for more information on SPI port timing.
PIN FUNCTIONS
This pin either may run continuously or be gated off in between
SPI transactions. See SPI Port section for more information on
SPI port timing.
All input pins have a logic threshold compatible withTTL input
levels and can therefore be used in systems with 3.3V logic. All
digital output levels are controlled by the ODVDD pin, which
may range from 2.7V to 5.5V, for compatibility with a wide
range of external devices. (See Pin Function Descriptions table.)
It must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction may take a different
number of CCLKs to complete, depending on the address and
read/write bit that are sent at the beginning of the SPI transaction.
Detailed SPI timing information is given in SPI Port section.
SDATA0, SDATA1, SDATA2—Serial Data Inputs
One of these three inputs is selected by an internal mux, set by
writing to Bits 7 and 6 in Control Register 2. Default is 00, which
selects SDATA0.The serial format is selected by writing to Bits 3–0
of Control Register 0. See SPI Read/Write Data Formats section
for recommendations on how to change input sources without
causing a click or pop noise.
RESETB
—Active Low Reset Signal After RESETB goes high, the AD1954 goes through an initial-
ization sequence where the program and parameter RAMs are
initialized with the contents of the on-board boot ROMs. All
SPI registers are set to 0, and the data RAMs are also zeroed.The
initialization is complete after 1024 MCLK cycles. Since the
MCLK IN FREQ SELECT (Bit 2 in Control Register 2) defaults
to 512
f
S at power-up, this initialization will proceed at the external MCLK rate and will take 1024 MCLK cycles to com-
plete, regardless of the absolute frequency of the external MCLK.
New values should not be written to the SPI port until the initial-
ization is complete.
LRCLK0, LRCLK1, LRCLK2—Left/Right Clocks for Framing the
Input Data
The active LRCLK input is selected by writing to Bits 7 and 6
in Control Register 2.The default is 00, which selects LRCLK0.
The interpretation of the LRCLK changes according to the serial
mode, set by writing to Control Register 0.
BCLK0, BCLK1, BCLK2—Serial Bit Clocks for Clocking in the
Serial Data
The active BCLK input is selected by writing to Bits 7 and 6 in
Control Register 2. Default is 00, which selects BCLK0.The
interpretation of BCLK changes according to the serial mode,
which is set by writing to Control Register 0.
ZEROFLAG
—Zero-Input Indicator This pin will go high if both serial inputs have been inactive (zero
data) for 1024 LRCLK cycles.This pin may be used to drive an
external mute FET for reduced noise during digital silence.This
pin also functions as a test out pin, controlled by the test register
at SPI Address 511
.
W
hile mos
t
T
e
st Modes are not useful to the
end user, one may be of some use. If theTest Register is pro-
grammed with the number 7 (decimal), the ZEROFLAG output
will be switched to the output of the internal pseudo-random noise
generator.This noise generator operates at a bit rate of 128
f
S
and has a repeat time of once per 224 cycles.This mode may be
used to generate white noise (or, with appropriate filtering, pink
noise) to be used as a test signal for measuring speakers or room
LRCLKOUT, BCLKOUT, SDATAOUT—Output of Mux that
Selects One of theThree Serial Input Groups
These pins may be used to send the selected serial input signals
to other external devices.This output pin is enabled by writing a
1 to Bit 8 of Control Register 2.The default mode is 0 or Off.
MCLK0, MCLK1, MCLK2—Master Clock Inputs
Active input selected by writing to Bits 5 and 4 of Control Regis-
ter 2.The default is 00, which selects MCLK0.The master clock
frequency must be either 256
f
S or 512
f
S, where fS is the input
sampling rate.The master clock frequency is programmed by
writing to Bit 2 of Control Register 2.The default is 0 (512
f
S).
See the Initialization section for recommendations concerning
how to change clock sources without causing an audio click or pop.
Note that since the default MCLK source pin is MCLK0, there
must be a clock signal present on this pin on power-up so that
the AD1954 can complete its initialization routine.
REV. A
ADI [ ADI ]
